module TimeMeasurement(
    input clk,
    input rst,
    input [1:0] opcode,
    output [31:0] ms_count
);
 
    reg [31:0] clk_counter_reg, clk_counter_nxt;
    reg [31:0] ms_count_reg, ms_count_nxt;
    reg running;
 
    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            clk_counter_reg <= 0;
            ms_count_reg <= 0;
        end else begin
            clk_counter_reg <= clk_counter_nxt;
            ms_count_reg <= ms_count_nxt;
        end
    end
 
    always @(*) begin
        clk_counter_nxt = clk_counter_reg;
        ms_count_nxt = ms_count_reg;
 
        if (running) begin
            if (clk_counter_reg == 2499) begin 
                clk_counter_nxt = 0;
                ms_count_nxt = ms_count_reg + 1;
            end else begin
                clk_counter_nxt = clk_counter_reg + 1;
            end
        end
 
        case (opcode)
            2'b01: running = 1;   // Start
            2'b11: running = 0;   // Pause
            2'b10: begin          // Stop
                running = 0;
                ms_count_nxt = 0;
            end
            default: running = 0; // Default state
        endcase
    end
 
    assign ms_count = ms_count_reg;
 
endmodule