root@renegade:~/tinymembench# ./tinymembench tinymembench v0.4.9 (simple benchmark for memory throughput and latency) ========================================================================== == Memory bandwidth tests == == == == Note 1: 1MB = 1000000 bytes == == Note 2: Results for 'copy' tests show how many bytes can be == == copied per second (adding together read and writen == == bytes would have provided twice higher numbers) == == Note 3: 2-pass copy means that we are using a small temporary buffer == == to first fetch data into it, and only then write it to the == == destination (source -> L1 cache, L1 cache -> destination) == == Note 4: If sample standard deviation exceeds 0.1%, it is shown in == == brackets == ========================================================================== C copy backwards : 1792.9 MB/s (1.3%) C copy backwards (32 byte blocks) : 1781.3 MB/s (1.1%) C copy backwards (64 byte blocks) : 1775.2 MB/s (1.3%) C copy : 1781.8 MB/s (1.5%) C copy prefetched (32 bytes step) : 1587.7 MB/s C copy prefetched (64 bytes step) : 1883.9 MB/s (1.4%) C 2-pass copy : 1989.5 MB/s (1.2%) C 2-pass copy prefetched (32 bytes step) : 1509.1 MB/s (1.2%) C 2-pass copy prefetched (64 bytes step) : 1445.8 MB/s (1.4%) C fill : 7692.9 MB/s (2.4%) C fill (shuffle within 16 byte blocks) : 7692.1 MB/s (2.1%) C fill (shuffle within 32 byte blocks) : 7681.1 MB/s (2.5%) C fill (shuffle within 64 byte blocks) : 7677.3 MB/s --- standard memcpy : 1705.0 MB/s standard memset : 7681.8 MB/s (2.4%) --- NEON LDP/STP copy : 1963.3 MB/s (2.2%) NEON LDP/STP copy pldl2strm (32 bytes step) : 1617.8 MB/s (1.3%) NEON LDP/STP copy pldl2strm (64 bytes step) : 1882.5 MB/s NEON LDP/STP copy pldl1keep (32 bytes step) : 2047.3 MB/s NEON LDP/STP copy pldl1keep (64 bytes step) : 2058.6 MB/s (1.3%) NEON LD1/ST1 copy : 1923.6 MB/s (1.4%) NEON STP fill : 7679.5 MB/s NEON STNP fill : 2641.5 MB/s (2.1%) ARM LDP/STP copy : 1969.1 MB/s (1.3%) ARM STP fill : 7683.4 MB/s (2.8%) ARM STNP fill : 2637.7 MB/s (0.6%) ========================================================================== == Framebuffer read tests. == == == == Many ARM devices use a part of the system memory as the framebuffer, == == typically mapped as uncached but with write-combining enabled. == == Writes to such framebuffers are quite fast, but reads are much == == slower and very sensitive to the alignment and the selection of == == CPU instructions which are used for accessing memory. == == == == Many x86 systems allocate the framebuffer in the GPU memory, == == accessible for the CPU via a relatively slow PCI-E bus. Moreover, == == PCI-E is asymmetric and handles reads a lot worse than writes. == == == == If uncached framebuffer reads are reasonably fast (at least 100 MB/s == == or preferably >300 MB/s), then using the shadow framebuffer layer == == is not necessary in Xorg DDX drivers, resulting in a nice overall == == performance improvement. For example, the xf86-video-fbturbo DDX == == uses this trick. == ========================================================================== NEON LDP/STP copy (from framebuffer) : 378.4 MB/s NEON LDP/STP 2-pass copy (from framebuffer) : 363.0 MB/s (1.0%) NEON LD1/ST1 copy (from framebuffer) : 102.8 MB/s NEON LD1/ST1 2-pass copy (from framebuffer) : 101.5 MB/s (0.6%) ARM LDP/STP copy (from framebuffer) : 200.0 MB/s (0.5%) ARM LDP/STP 2-pass copy (from framebuffer) : 195.7 MB/s (1.0%) ========================================================================== == Memory latency test == == == == Average time is measured for random memory accesses in the buffers == == of different sizes. The larger is the buffer, the more significant == == are relative contributions of TLB, L1/L2 cache misses and SDRAM == == accesses. For extremely large buffer sizes we are expecting to see == == page table walk with several requests to SDRAM for almost every == == memory access (though 64MiB is not nearly large enough to experience == == this effect to its fullest). == == == == Note 1: All the numbers are representing extra time, which needs to == == be added to L1 cache latency. The cycle timings for L1 cache == == latency can be usually found in the processor documentation. == == Note 2: Dual random read means that we are simultaneously performing == == two independent memory accesses at a time. In the case if == == the memory subsystem can't handle multiple outstanding == == requests, dual random read has the same timings as two == == single reads performed one after another. == ========================================================================== block size : single random read / dual random read, [MADV_NOHUGEPAGE] 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.1 ns / 0.1 ns 65536 : 4.9 ns / 8.4 ns 131072 : 7.6 ns / 11.7 ns 262144 : 10.3 ns / 15.6 ns 524288 : 56.0 ns / 88.2 ns 1048576 : 83.8 ns / 118.8 ns 2097152 : 98.8 ns / 131.8 ns 4194304 : 111.2 ns / 142.6 ns 8388608 : 118.3 ns / 148.7 ns 16777216 : 123.4 ns / 153.1 ns 33554432 : 126.8 ns / 156.4 ns 67108864 : 136.6 ns / 173.1 ns block size : single random read / dual random read, [MADV_HUGEPAGE] 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.1 ns / 0.1 ns 65536 : 4.9 ns / 8.4 ns 131072 : 7.6 ns / 11.7 ns 262144 : 10.3 ns / 15.2 ns 524288 : 55.9 ns / 88.1 ns 1048576 : 83.7 ns / 118.8 ns 2097152 : 97.8 ns / 130.4 ns 4194304 : 104.8 ns / 135.3 ns 8388608 : 108.1 ns / 137.4 ns 16777216 : 109.7 ns / 138.4 ns 33554432 : 110.5 ns / 138.9 ns 67108864 : 111.0 ns / 139.2 ns