module top1(output [31:0] result,
				output reg negative,
				output zero,
				output overflow,
				output carry,
				input [31:0] A,
				input [31:0] B,
				input control0,
				input control1
				);


wire w1,w2,w3,w4;
				
Pand nume_aici1(.out(w1),
				    .in1(A),
						.in2(B)
					);

Por nume_aici2(.out(w2),
				    .in1(A),
						.in2(B)
					);

addsub32b nume_aici3( .overflow(overflow),
				.carry(carry),
				.addsubresult(w3),
				.sel(control0),
				.a(A),
				.b(B)
						);
						
selector nume_aici4( .selout(w4),
							.control(control0),
							.input0(w1),
							.input1(w2)
						);
						
selector nume_aici5( .selout(result),
							.control(control1),
							.input0(w4),
							.input1(w3)
						);
always @(*)
begin
	if(result[31]==1)
		negative = 1;
	else
		negative = 0;
end

assign zero = ~result;


endmodule