#include <stm32f10x.h>

#define  DWLOS_C
#include "DWLOS_config.h"
#include "DWLOS.h"



void Idle (void)
 { }



void Init_DWLOS (void)
 {
  uint8_t 	index;

  for (index = 0; index < Task_Turn_Size; index ++)
   {
    Task_Turn [index] = &Idle;
   }

  for (index = 0; index < Timer_Turn_Size; index ++)
   {
    (pTimer_Turn + index) -> Task = &Idle;
    (pTimer_Turn + index) -> Time = 0;
   }

#if      LOG_ACTIVE
  Log_bank = 0;
  Log_index = 0;

  Set_Timer (Log_Out, LOG_DL_INTERVAL);
#endif

  LOG_ADD(PROG_START);

  RCC -> AHBENR |= RCC_AHBENR_DMA1EN;
  RCC -> APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_AFIOEN;
  RCC -> APB2ENR |= LED1_RCC | LED2_RCC | LED3_RCC | LED4_RCC;


  // LED 1
  LED1_GPIO &= ~(LED1_CNF);
  LED1_GPIO |= LED1_MODE;
  LED1_OFF;

  // LED 2
  LED2_GPIO &= ~(LED2_CNF);
  LED2_GPIO |= LED2_MODE;
  LED2_OFF;

  // LED 3
  LED3_GPIO &= ~(LED3_CNF);
  LED3_GPIO |= LED3_MODE;
  LED3_OFF;

  // LED 4
  LED4_GPIO &= ~(LED4_CNF);
  LED4_GPIO |= LED4_MODE;
  LED4_OFF;



// RX = PA10
  GPIOA -> CRH |= GPIO_CRH_CNF10_1;
  GPIOA -> CRH &= ~GPIO_CRH_CNF10_0;
  GPIOA -> CRH &= ~(GPIO_CRH_MODE10_1 | GPIO_CRH_MODE10_0);

// TX = PA9
  GPIOA -> CRH |= GPIO_CRH_CNF9_1;
  GPIOA -> CRH &= ~GPIO_CRH_CNF9_0;
  GPIOA -> CRH |= GPIO_CRH_MODE9_1 | GPIO_CRH_MODE9_0;


  NVIC_SetPriority (DMA1_Channel4_IRQn, USART_TX_PRIORITY);	// USART1 TX
  NVIC_EnableIRQ (DMA1_Channel4_IRQn);

  NVIC_SetPriority (DMA1_Channel5_IRQn, USART_RX_PRIORITY);	// USART1 RX
  NVIC_EnableIRQ (DMA1_Channel5_IRQn);


//  DMA1 Channel4 -- USART.TX
  USART1_Tx_DMA -> CCR &= ~DMA_CCR4_MEM2MEM;
  USART1_Tx_DMA -> CCR |= DMA_CCR4_PL_1;
  USART1_Tx_DMA -> CCR &= ~(DMA_CCR4_MSIZE_1 | DMA_CCR4_MSIZE_0);
  USART1_Tx_DMA -> CCR &= ~(DMA_CCR4_PSIZE_1 | DMA_CCR4_PSIZE_0);
  USART1_Tx_DMA -> CCR |= DMA_CCR4_MINC;
  USART1_Tx_DMA -> CCR &= ~DMA_CCR4_PINC;
  USART1_Tx_DMA -> CCR &= ~DMA_CCR4_CIRC;
  USART1_Tx_DMA -> CCR |= DMA_CCR4_DIR;
  USART1_Tx_DMA -> CPAR = USART1_BASE + 0x04;
  USART1_Tx_DMA_IT_ON;

  USART1_Tx_DMA -> CMAR = (uint32_t) USART1_Tx_Buffer;
  USART1_Tx_DMA -> CNDTR = 0; // USART1_Tx_Buffer_Size


//  DMA1 Channel5 -- USART.RX
  USART1_Rx_DMA -> CCR &= ~DMA_CCR5_MEM2MEM;
  USART1_Rx_DMA -> CCR |= DMA_CCR5_PL_1;
  USART1_Rx_DMA -> CCR &= ~(DMA_CCR5_MSIZE_1 | DMA_CCR5_MSIZE_0);
  USART1_Rx_DMA -> CCR &= ~(DMA_CCR5_PSIZE_1 | DMA_CCR5_PSIZE_0);
  USART1_Rx_DMA -> CCR |= DMA_CCR5_MINC;
  USART1_Rx_DMA -> CCR &= ~DMA_CCR5_PINC;
  USART1_Rx_DMA -> CCR &= ~DMA_CCR5_CIRC;
  USART1_Rx_DMA -> CCR &= ~DMA_CCR5_DIR;
  USART1_Rx_DMA -> CPAR = USART1_BASE + 0x04;
  USART1_Rx_DMA_IT_ON;

  USART1_Rx_DMA -> CMAR = (uint32_t) USART1_Rx_Buffer;
  USART1_Rx_DMA -> CNDTR = USART1_Rx_Buffer_size;


//  USART1 Configuration
  USART1 -> CR1 |= USART_CR1_UE;
//  USART1 -> CR1 |= USART_CR1_TXEIE;
//  USART1 -> CR1 |= USART_CR1_RXNEIE;
  USART1 -> CR1 &= ~USART_CR1_M;
  USART1 -> CR1 &= ~USART_CR1_PCE;
  USART1 -> CR1 |= USART_CR1_TE | USART_CR1_RE;
  USART1 -> CR3 |= USART_CR3_DMAT | USART_CR3_DMAR;
//  USART1 -> BRR |= (USART_BRR_DIV_Mantissa & (117 << 4)) | (USART_BRR_DIV_Fraction & 3); 	// 38.4k
  USART1 -> BRR |= (USART_BRR_DIV_Mantissa & (39 << 4)) | (USART_BRR_DIV_Fraction & 1); 	// 115.2k
//  USART1 -> BRR |= (USART_BRR_DIV_Mantissa & (19 << 4)) | (USART_BRR_DIV_Fraction & 9); 	// 230.4k

  USART1_Tx_DMA_OFF;
  USART1_Rx_DMA_OFF;
 }




void Set_Task (pFnk TS)
 {
  uint8_t	index = 0;

  while (Task_Turn [index] != &Idle)
   {
    index ++;
    if (index == Task_Turn_Size)
     {
      LOG_ADD(TASK_OVERFLOW);
      return;
     }
   }

  Task_Turn [index] = TS;
 }


void Set_Timer (pFnk TS, uint16_t newTime)
 {
  uint8_t	index = 0;
  uint8_t	Idle_i = 255;

  for (index = 0; index < Timer_Turn_Size; index ++)
   {
    if ((pTimer_Turn + index) -> Task == TS)
     {
      (pTimer_Turn + index) -> Time = newTime;
      return;
     }
    else if (((pTimer_Turn + index) -> Task == &Idle) && (Idle_i == 255)) 
     {
      Idle_i = index;
     }
   }

  if (Idle_i != 255)
   {
    (pTimer_Turn + Idle_i) -> Task = TS;
    (pTimer_Turn + Idle_i) -> Time = newTime;
   }
  else
   {
    LOG_ADD(TIMER_OVERFLOW);
    return;
   }
 }



void Task_Manager (void)
 {
  uint8_t	index = 0;
  pFnk		Task = &Idle;



  Task = Task_Turn [0];

  if (Task == &Idle)
    (Idle)();

  else
   {
    for (index = 0; index < Task_Turn_Size; index ++)
     {
      Task_Turn [index] = Task_Turn [index + 1];
     }

    Task_Turn [Task_Turn_Size - 1] = &Idle;
    (Task)();
   }
 }


void Timer_Manager (void)
 {
  uint8_t	index;

  for (index = 0; index < Timer_Turn_Size; index ++)
   {
    if ((pTimer_Turn + index) -> Task == &Idle)
      continue;
    if ((pTimer_Turn + index) -> Time != 1)
      (pTimer_Turn + index) -> Time --;

    else
     {
      Set_Task ((pTimer_Turn + index) -> Task);
      (pTimer_Turn + index) -> Task = &Idle;
     }
   }
 }


void Run_DWLOS (void)
 {
  /* Setup SysTick Timer for 1 msec interrupts  */
  SysTick_Config (DWLOS_TIM_PRESCALER);

  LOG_ADD(RUN_OS);
 }

void Stop_DWLOS (void)
 {
//  SysTick -> CTRL = ~(SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
  SysTick -> CTRL = 0x00;
  
  LOG_ADD(STOP_OS);
 }

void SysTick_Handler (void)
 {
  Timer_Manager ();
 }


void WDG_init (void)
 {
  // IWDG_WriteAccess_Enable
  IWDG -> KR = ((uint16_t)0x5555);

  // Set Prescaler
  IWDG -> PR = IWDG_PRESCALER;

  // Set Reload value
  IWDG -> RLR = IWDG_RELOAD;

  // Update IWDG
  WDG_reload ();

  // IWDG Enable
  IWDG -> KR = ((uint16_t)0xCCCC);
 }

void WDG_reload (void)
 {
  IWDG -> KR = ((uint16_t)0xAAAA);

  LOG_ADD(IWG_RELOAD);
 }


#if      LOG_ACTIVE
void Log_Out (void)
 {
  if (Log_index > 0)
   {
    USART1_Tx_DMA_OFF;
    USART1_Tx_DMA -> CMAR = (uint32_t) (pLog_arr + Log_bank);
    USART1_Tx_DMA -> CNDTR = Log_index;
    USART1_Tx_DMA_ON;

    Log_index = 0;
    Log_bank = (Log_bank ? 0 : LOG_BANK_SIZE);
   }

  Set_Timer (Log_Out, LOG_DL_INTERVAL);
 }


void Log_Add (uint8_t ch)
 {
  if (Log_index > (LOG_BANK_SIZE-5) && LOG_ACTIVE)
   {
    Log_Out ();
   }

  if (Log_index == LOG_BANK_SIZE)
    Log_index = 0;

  *(pLog_arr + Log_bank + Log_index) = ch;
  Log_index ++;
 }
#endif