module contador (input clk, reset, en, load, input [3:0] loadValue, output reg [3:0] Q);

    always @ (posedge clk or posedge reset) begin
        if (reset)
            Q <= 4'b0000;
        else if (load)
            Q <= loadValue;
        else if (en)
            Q <= Q + 1;
    end

endmodule

/*
module testbench();

    reg clk, reset, en, load;
    reg [3:0] loadValue;
    wire [3:0] Q;

    contador U1(clk, reset, en, load, loadValue, Q);

    initial begin
        clk = 0; reset = 0; en = 0; load = 0; loadValue = 4'b0000;
        #2
        reset = 1;
        #1
        reset = 0;
        #10
        en = 1;
        #50
        loadValue = 4'b1100;
        load = 1;
        #10
        load = 0;
        #50
        en = 0;
    end

    initial
        #150 $finish;

    initial begin
        $dumpfile("timing.vcd");
        $dumpvars(0, testbench);
    end

    always
        #5 clk = ~clk;

endmodule
*/