case 4'h10: begin
    data_register[7:0] <= ram_data_bus[7:0]
    address_bus_mux_force <= 1'b0;
    ram_chip_read <= 1'b1;
    ram_chip_cs <= 1'b1;
 end
 ...
 assign ram_address_bus[19:0] = address_bus_mux_force ?
                                 addr_to_red_into_data_register[19:0] :
                                 some_other_address[19:0];
 assign ram_chip_OE_pin = ram_chip_read;
 assign ram_chip_CS_pin = ram_chip_cs;