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Sep 27th, 2021
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  1. /***************************************************************************
  2.  *             __________               __   ___.
  3.  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
  4.  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
  5.  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
  6.  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  7.  *                     \/            \/     \/    \/            \/
  8.  * $Id$
  9.  *
  10.  * Copyright (C) 2007 by Rob Purchase
  11.  * Copyright © 2008 Rafaël Carré
  12.  *
  13.  * This program is free software; you can redistribute it and/or
  14.  * modify it under the terms of the GNU General Public License
  15.  * as published by the Free Software Foundation; either version 2
  16.  * of the License, or (at your option) any later version.
  17.  *
  18.  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19.  * KIND, either express or implied.
  20.  *
  21.  ****************************************************************************/
  22.  
  23. #include "config.h"
  24. #include "kernel.h"
  25. #include "system.h"
  26. #include "panic.h"
  27. #include "ascodec.h"
  28. #include "adc.h"
  29. #include "dma-target.h"
  30. #include "clock-target.h"
  31. #include "fmradio_i2c.h"
  32. #include "button.h"
  33. #include "backlight-target.h"
  34. #include "lcd.h"
  35.  
  36. struct mutex cpufreq_mtx;
  37.  
  38. /*  Charge Pump and Power management Settings  */
  39. #define AS314_CP_DCDC3_SETTING    \
  40.                ((0<<7) |  /* CP_SW  Auto-Switch Margin 0=200/300 1=150/255 */  \
  41.                 (0<<6) |  /* CP_on  0=Normal op 1=Chg Pump Always On  */       \
  42.                 (0<<5) |  /* LREG_CPnot  Always write 0 */                     \
  43.                 (0<<3) |  /* DCDC3p  BVDD setting 3.6/3.2/3.1/3.0  */          \
  44.                 (1<<2) |  /* LREG_off 1=Auto mode switching 0=Length Reg only*/\
  45.                 (0<<0) )  /* CVDDp  Core Voltage Setting 1.2/1.15/1.10/1.05*/
  46.  
  47. #define CVDD_1_20          0
  48. #define CVDD_1_15          1
  49. #define CVDD_1_10          2
  50. #define CVDD_1_05          3
  51.  
  52. #define default_interrupt(name) \
  53.   extern __attribute__((weak,alias("UIRQ"))) void name (void)
  54.  
  55. #if CONFIG_USBOTG != USBOTG_DESIGNWARE
  56. static void UIRQ (void) __attribute__((interrupt ("IRQ")));
  57. #endif
  58. void irq_handler(void) __attribute__((naked, interrupt ("IRQ")));
  59. void fiq_handler(void) __attribute__((interrupt ("FIQ")));
  60.  
  61. default_interrupt(INT_WATCHDOG);
  62. default_interrupt(INT_TIMER1);
  63. default_interrupt(INT_TIMER2);
  64. default_interrupt(INT_USB_FUNC);
  65. default_interrupt(INT_DMAC);
  66. default_interrupt(INT_NAND);
  67. default_interrupt(INT_IDE);
  68. default_interrupt(INT_MCI0);
  69. default_interrupt(INT_MCI1);
  70. default_interrupt(INT_AUDIO);
  71. default_interrupt(INT_SSP);
  72. default_interrupt(INT_I2C_MS);
  73. default_interrupt(INT_I2C_AUDIO);
  74. default_interrupt(INT_I2SIN);
  75. default_interrupt(INT_I2SOUT);
  76. default_interrupt(INT_UART);
  77. default_interrupt(INT_GPIOD);
  78. default_interrupt(RESERVED1); /* Interrupt 17 : unused */
  79. default_interrupt(INT_CGU);
  80. default_interrupt(INT_MEMORY_STICK);
  81. default_interrupt(INT_DBOP);
  82. default_interrupt(RESERVED2); /* Interrupt 21 : unused */
  83. default_interrupt(RESERVED3); /* Interrupt 22 : unused */
  84. default_interrupt(RESERVED4); /* Interrupt 23 : unused */
  85. default_interrupt(RESERVED5); /* Interrupt 24 : unused */
  86. default_interrupt(RESERVED6); /* Interrupt 25 : unused */
  87. default_interrupt(RESERVED7); /* Interrupt 26 : unused */
  88. default_interrupt(RESERVED8); /* Interrupt 27 : unused */
  89. default_interrupt(RESERVED9); /* Interrupt 28 : unused */
  90. /* INT_GPIOA is declared in this file */
  91. void INT_GPIOA(void);
  92. default_interrupt(INT_GPIOB);
  93. default_interrupt(INT_GPIOC);
  94.  
  95. static const char const irqname[][9] =
  96. {
  97.     "WATCHDOG", "TIMER1", "TIMER2", "USB", "DMAC", "NAND",
  98.     "IDE", "MCI0", "MCI1", "AUDIO", "SSP", "I2C_MS",
  99.     "I2C_AUDIO", "I2SIN", "I2SOUT", "UART", "GPIOD", "RESERVD1",
  100.     "CGU", "MS", "DBOP", "RESERVD2", "RESERVD3", "RESERVD4",
  101.     "RESERVD5", "RESERVD6", "RESERVD7", "RESERVD8", "RESERVD9", "GPIOA",
  102.     "GPIOB", "GPIOC"
  103. };
  104.  
  105. static void UIRQ(void)
  106. {
  107.     bool masked = false;
  108.     int status = VIC_IRQ_STATUS;
  109.     if(status == 0)
  110.     {
  111.         status = VIC_RAW_INTR; /* masked interrupts */
  112. #if CONFIG_USBOTG == USBOTG_DESIGNWARE
  113.         /* spurious interrupts from USB are expected */
  114.         if (status & INTERRUPT_USB)
  115.             return;
  116. #endif
  117.         masked = true;
  118.     }
  119.  
  120.     if(status == 0)
  121.         panicf("Unhandled IRQ (source unknown!)");
  122.  
  123.     unsigned irq_no = 31 - __builtin_clz(status);
  124.  
  125.     panicf("Unhandled %smasked IRQ %02X: %s (status 0x%8X)",
  126.            masked ? "" : "un", irq_no, irqname[irq_no], status);
  127. }
  128.  
  129. /* Vectored interrupts (16 available) */
  130. static const struct { int source; void (*isr) (void); } vec_int_srcs[] =
  131. {
  132.     /* Highest priority at the top of the list */
  133. #if defined(HAVE_HOTSWAP) || defined(HAVE_RDS_CAP) || \
  134.     (defined(SANSA_FUZEV2) && !INCREASED_SCROLLWHEEL_POLLING)
  135.     /* If GPIOA ISR is interrupted, things seem to go wonky ?? */
  136.     { INT_SRC_GPIOA, INT_GPIOA },
  137. #endif
  138. #ifdef HAVE_RECORDING
  139.     { INT_SRC_I2SIN, INT_I2SIN }, /* For recording */
  140. #endif
  141.     { INT_SRC_DMAC, INT_DMAC }, /* Playback follows recording */
  142.     { INT_SRC_NAND, INT_NAND },
  143. #if (defined HAVE_MULTIDRIVE  && CONFIG_CPU == AS3525)
  144.     { INT_SRC_MCI0, INT_MCI0 },
  145. #endif
  146.     { INT_SRC_USB, INT_USB_FUNC, },
  147.     { INT_SRC_TIMER1, INT_TIMER1 },
  148.     { INT_SRC_TIMER2, INT_TIMER2 },
  149.     { INT_SRC_I2C_AUDIO, INT_I2C_AUDIO },
  150.     { INT_SRC_AUDIO, INT_AUDIO },
  151.     /* Lowest priority at the end of the list */
  152. };
  153.  
  154. static void setup_vic(void)
  155. {
  156.     CGU_PERI |= CGU_VIC_CLOCK_ENABLE; /* enable VIC */
  157.     VIC_INT_EN_CLEAR = 0xffffffff; /* disable all interrupt lines */
  158.     VIC_INT_SELECT = 0; /* only IRQ, no FIQ */
  159.  
  160.     *VIC_DEF_VECT_ADDR = UIRQ;
  161.  
  162.     for(unsigned int i = 0; i < ARRAYLEN(vec_int_srcs); i++)
  163.     {
  164.         VIC_VECT_ADDRS[i] = vec_int_srcs[i].isr;
  165.         VIC_VECT_CNTLS[i] = (1<<5) | vec_int_srcs[i].source;
  166.     }
  167.  
  168.     /* Reset priority hardware */
  169.     for(unsigned int i = 0; i < 32; i++)
  170.         *VIC_VECT_ADDR = 0;
  171. }
  172.  
  173. void INT_GPIOA(void)
  174. {
  175. #ifdef HAVE_HOTSWAP
  176.     void sd_gpioa_isr(void);
  177.     sd_gpioa_isr();
  178. #endif
  179. #if defined(SANSA_FUZEV2) && !INCREASED_SCROLLWHEEL_POLLING
  180.     void button_gpioa_isr(void);
  181.     button_gpioa_isr();
  182. #endif
  183. #ifdef HAVE_RDS_CAP
  184.     void tuner_isr(void);
  185.     tuner_isr();
  186. #endif
  187. }
  188.  
  189. void irq_handler(void)
  190. {
  191.     /* Worst-case IRQ stack usage with 10 vectors:
  192.      * 10*4*10 = 400 bytes (100 words)
  193.      *
  194.      * No SVC stack is used by pro/epi-logue code
  195.      */
  196.     asm volatile (
  197.         "sub    lr, lr, #4               \n" /* Create return address */
  198.         "stmfd  sp!, { r0-r5, r12, lr }  \n" /* Save what gets clobbered */
  199.         "ldr    r0, =0xc6010030          \n" /* Obtain VIC address (before SPSR read!) */
  200.         "ldr    r12, [r0]                \n" /* Load Vector */
  201.         "mrs    r1, spsr                 \n" /* Save SPSR_irq */
  202.         "stmfd  sp!, { r0-r1 }           \n" /* Must have something bet. mrs and msr */
  203.         "msr    cpsr_c, #0x13            \n" /* Switch to SVC mode, enable IRQ */
  204.         "and    r4, sp, #4               \n" /* Align SVC stack to 8 bytes, save */
  205.         "sub    sp, sp, r4               \n"
  206.         "mov    r5, lr                   \n" /* Save lr_SVC */
  207. #if ARM_ARCH >= 5
  208.         "blx    r12                      \n" /* Call handler */
  209. #else
  210.         "mov    lr, pc                   \n"
  211.         "bx     r12                      \n"
  212. #endif
  213.         "add    sp, sp, r4               \n" /* Undo alignment fudge */
  214.         "mov    lr, r5                   \n" /* Restore lr_SVC */
  215.         "msr    cpsr_c, #0x92            \n" /* Mask IRQ, return to IRQ mode */
  216.         "ldmfd  sp!, { r0-r1 }           \n" /* Pop VIC address, SPSR_irq */
  217.         "str    r0, [r0]                 \n" /* Ack end of ISR to VIC  */
  218.         "msr    spsr_cxsf, r1            \n" /* Restore SPSR_irq */
  219.         "ldmfd  sp!, { r0-r5, r12, pc }^ \n" /* Restore regs, and RFE */
  220.     );
  221. }
  222.  
  223. void fiq_handler(void)
  224. {
  225. }
  226.  
  227. #if defined(SANSA_C200V2)
  228. int c200v2_variant;
  229.  
  230. static void check_model_variant(void)
  231. {
  232.     unsigned int i;
  233.     unsigned int saved_dir = GPIOA_DIR;
  234.  
  235.     /* Make A7 input */
  236.     GPIOA_DIR &= ~(1<<7);
  237.     /* wait a little to allow the pullup/pulldown resistor
  238.      * to charge the input capacitance */
  239.     for (i=0; i<1000; i++) asm volatile ("nop\n");
  240.     /* read the pullup/pulldown value on A7 to determine the variant */
  241.     c200v2_variant = !GPIOA_PIN(7);
  242.     GPIOA_DIR = saved_dir;
  243. }
  244. #elif defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
  245. int amsv2_variant;
  246.  
  247. static void check_model_variant(void)
  248. {
  249.     GPIOB_DIR &= ~(1<<5);
  250.     amsv2_variant = !!GPIOB_PIN(5);
  251. }
  252. #else
  253. static inline void check_model_variant(void)
  254. {
  255. }
  256. #endif /* model selection */
  257.  
  258. void system_init(void)
  259. {
  260. #if CONFIG_CPU == AS3525v2
  261.     CCU_SRC = 0x57D7BF0;
  262. #else
  263.     CCU_SRC = 0x1fffff0
  264.         & ~CCU_SRC_IDE_EN; /* FIXME */
  265. #endif
  266.  
  267.     unsigned int reset_loops = 640;
  268.     while(reset_loops--)
  269.         CCU_SRL = CCU_SRL_MAGIC_NUMBER;
  270.     CCU_SRC = CCU_SRL = 0;
  271.  
  272.     CCU_SCON = 1; /* AHB master's priority configuration :
  273.                      TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
  274.  
  275.     CGU_PROC = 0;           /* fclk 24 MHz */
  276. #if CONFIG_CPU == AS3525v2
  277.     /* pclk is always based on PLLA, since we don't know the current PLLA speed,
  278.      * avoid having pclk too fast and hope it's not too low */
  279.     CGU_PERI |= 0xf << 2;   /* pclk lowest */
  280. #else
  281.     CGU_PERI &= ~0x7f;      /* pclk 24 MHz */
  282. #endif
  283.  
  284.     /* bits 31:30 should be set to 0 in arm926-ejs */
  285.     asm volatile(
  286.         "mrc p15, 0, r0, c1, c0   \n"      /* control register */
  287.         "bic r0, r0, #3<<30       \n"      /* clears bus bits : sets fastbus */
  288.         "mcr p15, 0, r0, c1, c0   \n"
  289.         : : : "r0" );
  290.  
  291.     CGU_COUNTA = CGU_LOCK_CNT;
  292.     CGU_PLLA = AS3525_PLLA_SETTING;
  293.     CGU_PLLASUP = 0;                          /* enable PLLA */
  294.     while(!(CGU_INTCTRL & CGU_PLLA_LOCK));    /* wait until PLLA is locked */
  295.  
  296. #if AS3525_MCLK_SEL == AS3525_CLK_PLLB
  297.     CGU_COUNTB = CGU_LOCK_CNT;
  298.     CGU_PLLB = AS3525_PLLB_SETTING;
  299.     CGU_PLLBSUP = 0;                          /* enable PLLB */
  300.     while(!(CGU_INTCTRL & CGU_PLLB_LOCK));    /* wait until PLLB is locked */
  301. #endif
  302.  
  303.     /*  Set FCLK frequency */
  304.     CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
  305.                 (AS3525_FCLK_PREDIV  << 2) |
  306.                  AS3525_FCLK_SEL);
  307.  
  308.     /*  Set PCLK frequency */
  309.     CGU_PERI = ((CGU_PERI & ~0x7F)  |       /* reset divider & clksel bits */
  310.                  (AS3525_PCLK_DIV0 << 2) |
  311. #if CONFIG_CPU == AS3525
  312.                  (AS3525_PCLK_DIV1 << 6) |
  313. #endif
  314.                   AS3525_PCLK_SEL);
  315.  
  316.     CGU_PERI |= CGU_ROM_ENABLE; /* needed for rebooting */
  317.  
  318. #if 0 /* the GPIO clock is already enabled by the dualboot function */
  319.     CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
  320. #endif
  321.  
  322.     /* enable timer interface for TIMER1 & TIMER2 */
  323.     CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE;
  324.  
  325.     setup_vic();
  326.  
  327.     dma_init();
  328. }
  329.  
  330. /* this is called after kernel and threading are initialized */
  331. void kernel_device_init(void)
  332. {
  333.     mutex_init(&cpufreq_mtx);
  334.  
  335.     ascodec_init();
  336.  
  337.     /*  Initialize power management settings */
  338. #ifdef HAVE_AS3543
  339.     /* PLL:       disable audio PLL, we use MCLK already */
  340.     ascodec_write_pmu(0x1A, 7, 0x02);
  341.     /* DCDC_Cntr: set switching speed of CVDD1/2 power supplies to 1 MHz,
  342.        immediate change */
  343.     ascodec_write_pmu(0x17, 7, 0x30);
  344.     /* Out_Cntr2: set drive strength of 24 MHz and 32 kHz clocks to 1 mA */
  345.     ascodec_write_pmu(0x1A, 2, 0xCC);
  346.     /* CHGVBUS2:  set VBUS threshold to 3.18V and EOC threshold to 30% CC */
  347.     ascodec_write_pmu(0x19, 2, 0x41);
  348.     /* PVDD1:     set PVDD1 power supply to 2.5 V */
  349.     ascodec_write_pmu(0x18, 1, 0x35);
  350.     /* AVDD17:    set AVDD17 power supply to 2.5V */
  351.     ascodec_write_pmu(0x18, 7, 0x31);
  352.     /* CVDD2:     set CVDD2 power supply (digital for DAC/SD/etc) to 2.75V */
  353.     ascodec_write_pmu(0x17, 2, 0x80 | 115);
  354. #else /* HAVE_AS3543 */
  355.     ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING);
  356. #endif /* HAVE_AS3543 */
  357.  
  358. #ifndef BOOTLOADER
  359.     /* setup isr for microsd monitoring and for fuzev2 scrollwheel irq */
  360. #if defined(HAVE_HOTSWAP) || \
  361.     (defined(SANSA_FUZEV2) && !INCREASED_SCROLLWHEEL_POLLING)
  362.     VIC_INT_ENABLE = (INTERRUPT_GPIOA);
  363.     /* pin selection for irq happens in the drivers */
  364. #endif
  365.  
  366. #if CONFIG_TUNER
  367.     fmradio_i2c_init();
  368. #endif
  369. #endif /* !BOOTLOADER */
  370.     check_model_variant();
  371. }
  372.  
  373. void system_reboot(void)
  374. {
  375.     backlight_hw_off();
  376.  
  377.     disable_irq();
  378.  
  379.     /* use watchdog to reset */
  380.     CGU_PERI |= (CGU_WDOCNT_CLOCK_ENABLE | CGU_WDOIF_CLOCK_ENABLE);
  381.     WDT_LOAD = 1; /* set counter to 1 */
  382.     WDT_CONTROL = 3; /* enable watchdog counter & reset */
  383.     while(1);
  384. }
  385.  
  386. void system_exception_wait(void)
  387. {
  388.     /* make sure lcd+backlight are on */
  389.     _backlight_panic_on();
  390.     /* make sure screen content is up to date */
  391.     lcd_update();
  392.     /* wait until button release (if a button is pressed) */
  393.     while(button_read_device());
  394.     /* then wait until next button press */
  395.     while(!button_read_device());
  396. }
  397.  
  398. int system_memory_guard(int newmode)
  399. {
  400.     (void)newmode;
  401.     return 0;
  402. }
  403.  
  404. /* usecs may be at most 2^32/248 (17 seconds) for 248MHz max cpu freq */
  405. void udelay(unsigned usecs)
  406. {
  407.     unsigned cycles_per_usec;
  408.     unsigned delay;
  409.  
  410.     if (cpu_frequency == CPUFREQ_MAX) {
  411.         cycles_per_usec = (CPUFREQ_MAX + 999999) / 1000000;
  412.     } else {
  413.         cycles_per_usec = (CPUFREQ_NORMAL + 999999) / 1000000;
  414.     }
  415.  
  416.     delay = (usecs * cycles_per_usec + 3) / 4;
  417.  
  418.     asm volatile(
  419.         "1: subs %0, %0, #1  \n"    /* 1 cycle  */
  420.         "   bne  1b          \n"    /* 3 cycles */
  421.         : : "r"(delay)
  422.     );
  423. }
  424.  
  425. #ifndef BOOTLOADER
  426. #ifdef HAVE_ADJUSTABLE_CPU_FREQ
  427. bool set_cpu_frequency__lock(void)
  428. {
  429.     if (get_processor_mode() != CPU_MODE_THREAD_CONTEXT)
  430.         return false;
  431.  
  432.     mutex_lock(&cpufreq_mtx);
  433.     return true;
  434. }
  435.  
  436. void set_cpu_frequency__unlock(void)
  437. {
  438.     mutex_unlock(&cpufreq_mtx);
  439. }
  440.  
  441. #if CONFIG_CPU == AS3525
  442. void set_cpu_frequency(long frequency)
  443. {
  444.     if (frequency == cpu_frequency)
  445.     {
  446.         /* avoid redundant activity */
  447.     }
  448.     else // if(frequency == CPUFREQ_MAX)
  449.     {
  450. #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
  451.         /* Increasing frequency so boost voltage before change */
  452.         ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20));
  453.  
  454.         /* Some players run a bit low so use 1.175 volts instead of 1.20  */
  455.         /* Wait for voltage to be at least 1.175v before making fclk > 200 MHz */
  456.         while(adc_read(ADC_CVDD) < 470); /* 470 * .0025 = 1.175V */
  457. #endif  /*  HAVE_ADJUSTABLE_CPU_VOLTAGE */
  458.  
  459.         CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
  460.                     (AS3525_FCLK_PREDIV  << 2) |
  461.                      AS3525_FCLK_SEL);
  462.  
  463.         asm volatile(
  464.             "mrc p15, 0, r0, c1, c0  \n"
  465.             "orr r0, r0, #3<<30      \n"   /* asynchronous bus clocking */
  466.             /* synchronous bus clocking had issues on some players */
  467.             "mcr p15, 0, r0, c1, c0  \n"
  468.             : : : "r0" );
  469.  
  470.         cpu_frequency = CPUFREQ_MAX;
  471.     }
  472.     else
  473.     {
  474.         asm volatile(
  475.             "mrc p15, 0, r0, c1, c0  \n"
  476.             "bic r0, r0, #3<<30      \n"     /* fastbus clocking */
  477.             "mcr p15, 0, r0, c1, c0  \n"
  478.             : : : "r0" );
  479.  
  480.         /* FCLK is unused so put it to the lowest freq we can */
  481.         CGU_PROC = ((0xf << 4) | (0x3 << 2) | AS3525_CLK_MAIN);
  482.  
  483. #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
  484.         /* Decreasing frequency so reduce voltage after change */
  485.         ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10));
  486. #endif  /*  HAVE_ADJUSTABLE_CPU_VOLTAGE */
  487.  
  488.         cpu_frequency = CPUFREQ_NORMAL;
  489.     }
  490. }
  491. #else   /* as3525v2  */
  492. void set_cpu_frequency(long frequency)
  493. {
  494.     if (frequency == cpu_frequency)
  495.     {
  496.         /* avoid redundant activity */
  497.     }
  498.     else if(frequency == CPUFREQ_MAX)
  499.     {
  500. #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
  501.         /* Set CVDD1 power supply */
  502.         ascodec_write_pmu(0x17, 1, 0x80 | 47);
  503.         /* dely for voltage rising */
  504.         udelay(50);
  505. #endif
  506.         CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
  507.                     (AS3525_FCLK_PREDIV  << 2) |
  508.                     AS3525_FCLK_SEL);
  509.  
  510.         cpu_frequency = CPUFREQ_MAX;
  511.     }
  512. #if 0
  513.     else
  514.     {
  515.         CGU_PROC = ((AS3525_FCLK_POSTDIV_UNBOOSTED << 4) |
  516.                     (AS3525_FCLK_PREDIV  << 2) |
  517.                     AS3525_FCLK_SEL);
  518.  
  519.         cpu_frequency = CPUFREQ_NORMAL;
  520.  
  521.         /* Set CVDD1 power supply */
  522. #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
  523. #if defined(SANSA_CLIPZIP)
  524.         ascodec_write_pmu(0x17, 1, 0x80 | 20);
  525. #elif defined(SANSA_CLIPPLUS)
  526.         if (amsv2_variant)
  527.             ascodec_write_pmu(0x17, 1, 0x80 | 22);
  528.         else
  529.             ascodec_write_pmu(0x17, 1, 0x80 | 26);
  530. #elif defined(SANSA_FUZEV2)
  531.         /*Some FuzeV2 devices have trouble reading SD at low voltage*/
  532.     ascodec_write_pmu(0x17, 1, 0x80 | 26);
  533. #else
  534.         ascodec_write_pmu(0x17, 1, 0x80 | 22);
  535. #endif
  536. #endif
  537.     }
  538. #endif
  539. }
  540. #endif
  541.  
  542. #endif /* HAVE_ADJUSTABLE_CPU_FREQ */
  543. #endif /* !BOOTLOADER */
  544.  
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