module lab(x, y, m, isof, out);
input [3:0] x,y;
input m;
output [4:0] out;
output isof;

reg [4:0] out;
reg isof;

always @ (x or y or m)
begin
out = x+y;
if ((m==1'b1) && (out<x))
isof = 1'b1;
if ((m==1'b0) && (out>x))
isof = 1'b0;
end
endmodule