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Corrected shmem device tree

botsnlinux
Apr 10th, 2018
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  1. /include/ "system-conf.dtsi"
  2. #include <dt-bindings/phy/phy.h>
  3.  
  4. / {
  5. model = "Avnet UltraZed-3EG";
  6. chosen {
  7. bootargs = "earlycon=cdns,mmio,0xFF000000,115200n8 root=/dev/mmcblk1p2 rw rootwait earlyprintk cma=512m";
  8. };
  9.  
  10. /* Stuff for using the R5 with remoteproc
  11. * Copied from Xilinx wiki: http://www.wiki.xilinx.com/OpenAMP+2017.2
  12. */
  13. reserved-memory {
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. ranges;
  17. rproc_0_reserved: rproc@3e0000000 {
  18. no-map;
  19. /* DDR memory reserved for RPU firmware.
  20. * If you want to use predefined shared memory,
  21. * you should also reserved them here.
  22. */
  23. reg = <0x0 0x3e000000 0x0 0x1000000>;
  24. };
  25. };
  26.  
  27. power-domains {
  28. /* For TCM memories, you will need specify the power domain
  29. * IDs. As APU will need to use the power domain ID to request
  30. * access through PMU FW.
  31. */
  32. pd_r5_0: pd_r5_0 {
  33. #power-domain-cells = <0x0>;
  34. pd-id = <0x7>;
  35. };
  36. pd_tcm_0_a: pd_tcm_0_a {
  37. #power-domain-cells = <0x0>;
  38. pd-id = <0xf>;
  39. };
  40. pd_tcm_0_b: pd_tcm_0_b {
  41. #power-domain-cells = <0x0>;
  42. pd-id = <0x10>;
  43. };
  44.  
  45. };
  46.  
  47. amba {
  48. /* You will need to specify the firmware memory as "mmio-sram". */
  49. r5_0_tcm_a: tcm@ffe00000 {
  50. compatible = "mmio-sram";
  51. reg = <0 0xFFE00000 0x0 0x10000>;
  52. pd-handle = <&pd_tcm_0_a>;
  53. };
  54. r5_0_tcm_b: tcm@ffe20000 {
  55. compatible = "mmio-sram";
  56. reg = <0 0xFFE20000 0x0 0x10000>;
  57. pd-handle = <&pd_tcm_0_b>;
  58. };
  59.  
  60. /* DRAM reserved for executable
  61. * the address must match the reserved memory section above */
  62. elf_ddr_0: ddr@3e000000 {
  63. compatible = "mmio-sram";
  64. reg = <0 0x3e000000 0x0 0x100000>;
  65. };
  66.  
  67. /* And finally the actual remoteproc entry */
  68. /* This is for 2017.2; note that there are some small (but critical)
  69. * changes in 2017.3 */
  70. test_r50: zynqmp_r5_rproc@0 {
  71. compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
  72. reg = <0x0 0xff9a0100 0 0x100>, <0x0 0xff340000 0 0x100>, <0x0 0xff9a0000 0 0x100>;
  73. reg-names = "rpu_base", "ipi", "rpu_glbl_base";
  74. dma-ranges;
  75. core_conf = "split0";
  76.  
  77. /* Specify the firmware memories here */
  78. sram_0 = <&r5_0_tcm_a>;
  79. sram_1 = <&r5_0_tcm_b>;
  80. sram_2 = <&elf_ddr_0>;
  81. pd-handle = <&pd_r5_0>;
  82. interrupt-parent = <&gic>;
  83. interrupts = <0 29 4>;
  84. } ;
  85.  
  86. /* Shared memory */
  87. shm0: shm@0 {
  88. compatible = "shm_uio";
  89. reg = <0x0 0x3e800000 0x0 0x100000>;
  90. };
  91.  
  92. };
  93.  
  94. /* END of R5 remoteproc stuff */
  95.  
  96. };
  97. /* END of root node; everything below is a reference to something that already
  98. * exists in the tree. */
  99.  
  100.  
  101. /* Ethernet config for production silicon */
  102. //&gem3 {
  103. // status = "okay";
  104. // local-mac-address = [00 0a 35 00 02 90];
  105. // phy-mode = "rgmii-id";
  106. // phy-handle = <&phy0>;
  107. // phy0: phy@9 {
  108. // reg = <0x9>;
  109. // ti,rx-internal-delay = <0x5>;
  110. // ti,tx-internal-delay = <0x5>;
  111. // ti,fifo-depth = <0x1>;
  112. // };
  113. //};
  114.  
  115. /* Ethernet for ES1 silicon */
  116. &gem3 {
  117. status = "okay";
  118. local-mac-address = [00 0a 35 00 02 90];
  119. phy-mode = "rgmii-id";
  120. phy-handle = <&phy0>;
  121. phy0: phy@5 {
  122. reg = <0x5>;
  123. ti,rx-internal-delay = <0x5>;
  124. ti,tx-internal-delay = <0x5>;
  125. ti,fifo-depth = <0x1>;
  126. };
  127. };
  128.  
  129. // Hard I2C controller and the DP clock generator connected to it
  130. &i2c1 {
  131. status = "okay";
  132. clock-frequency = <400000>;
  133. i2cswitch@70 { /* u7 */
  134. compatible = "nxp,pca9543";
  135. #address-cells = <1>;
  136. #size-cells = <0>;
  137. reg = <0x70>;
  138. i2c@0 { /* i2c mw 70 0 1 */
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. reg = <0>;
  142. // TODO: the other board has an eeprom@52 (U5 on IOCC)?
  143. eeprom: eeprom1@50 { /* 2048-bit (8-bit X 256) IIC_EEPROM - SOM U8 */
  144. compatible = "at,24c02";
  145. reg = <0x50>;
  146. };
  147.  
  148. macid: eeprom2@51 { /* IIC_MAC_ID - IOCC U5 */
  149. compatible = "at,24mac402";
  150. reg = <0x51>;
  151. };
  152.  
  153. idt5901: clock-generator@6a { /* IDT 5P49V5935 clock generator - IOCC U1 */
  154. #clock-cells = <0>;
  155. compatible = "idt,idt5901";
  156. reg = <0x6a>;
  157. input-freq = <25000000>;
  158. clk-freq = <75000000>;
  159. output-num = <4>;
  160. };
  161. };
  162. i2c@1 { /* i2c mw 70 0 2 */
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. reg = <1>;
  166. /* SMBUS */
  167. };
  168. };
  169. };
  170.  
  171. &qspi {
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. status = "okay";
  175. flash0: flash@0 {
  176. compatible = "micron,n25q256a"; /* 32MB */
  177. #address-cells = <1>;
  178. #size-cells = <1>;
  179. reg = <0x0>;
  180. spi-tx-bus-width = <1>;
  181. spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  182. spi-max-frequency = <108000000>; /* Based on DC1 spec */
  183. partition@qspi-boot {
  184. label = "qspi-boot";
  185. reg = <0x0 0x780000>;
  186. };
  187. partition@qspi-bootenv {
  188. label = "qspi-bootenv";
  189. reg = <0x780000 0x80000>;
  190. };
  191. partition@qspi-linux {
  192. label = "qspi-linux";
  193. reg = <0x800000 0x3800000>;
  194. };
  195. };
  196. };
  197.  
  198. /* SD0 eMMC, 8-bit wide data bus */
  199. &sdhci0 {
  200. status = "okay";
  201. bus-width = <8>;
  202. clock-frequency = <199998006>;
  203. max-frequency = <50000000>;
  204. };
  205.  
  206. /* SD1 with level shifter */
  207. &sdhci1 {
  208. status = "okay";
  209. no-1-8-v; /* for 1.0 silicon */
  210. xlnx,mio_bank = <1>;
  211. disable-wp;
  212. };
  213.  
  214. /* ULPI SMSC USB3320 */
  215. &usb0 {
  216. status = "okay";
  217. };
  218.  
  219. &dwc3_0 {
  220. status = "okay";
  221. dr_mode = "host";
  222. phy-names = "usb3-phy";
  223. };
  224.  
  225. /* DisplayPort Configuration */
  226. &xilinx_drm {
  227. status = "okay";
  228. clocks = <&idt5901>;
  229. xlnx,vid-clk-pl;
  230. planes {
  231. xlnx,pixel-format = "argb8888";
  232. };
  233. };
  234.  
  235. &xlnx_dp {
  236. status = "okay";
  237. phy-names = "dp-phy0", "dp-phy1";
  238. phys = <&lane3 PHY_TYPE_DP 0 3 27000000>;
  239. };
  240. /* For IOCC:
  241. &xlnx_dp {
  242. status = "okay";
  243. phy-names = "dp-phy0", "dp-phy1";
  244. phys = <&lane3 PHY_TYPE_DP 0 3 27000000>, <&lane2 PHY_TYPE_DP 1 3 27000000>;
  245. };
  246. */
  247.  
  248. &xlnx_dp_sub {
  249. status = "okay";
  250. xlnx,vid-clk-pl;
  251. xlnx,gfx-fmt = "argb8888";
  252. };
  253.  
  254. &xlnx_dp_snd_card {
  255. status = "okay";
  256. };
  257.  
  258. &xlnx_dp_snd_codec0 {
  259. status = "okay";
  260. };
  261.  
  262. &xlnx_dp_snd_pcm0 {
  263. status = "okay";
  264. };
  265.  
  266. &xlnx_dp_snd_pcm1 {
  267. status = "okay";
  268. };
  269.  
  270. &xlnx_dpdma {
  271. status = "okay";
  272. };
  273. /* END DisplayPort config */
  274.  
  275. /* Turn all the fabric clocks on, because petalinux tries to turn them off
  276. * to save power. */
  277. &clkc {
  278. fclk-enable = <0xf>;
  279. };
  280.  
  281. &fclk0 {
  282. status = "okay";
  283. };
  284.  
  285. &fclk1 {
  286. status = "okay";
  287. };
  288.  
  289. &fclk2 {
  290. status = "okay";
  291. };
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