library ieee ;  use ieee.std_logic_1164.all;
        use ieee.numeric_std.all;
library work ; use work.basic.all;

entity fsm is
    port(   Convert_i,
            Clk_i       : in std_logic;
            Data_id     : in std_logic_vector(7 downto 0);
            S4_o, S3n_o,
            S2n_o, S1_o,
            Busy_o,
            New_data_o,
            Reset_i     : out std_logic

        );
end;

architecture Behavior of fsm is

    type State_type is (Zero, Disconnect_1, Disconnect_2, Sample, Compute, Update, Next_Byte);

    signal Next_sate, Current_state : State_type;
    signal inc_cnt_s                : std_logic;
    signal N_s                      : integer range 8 to 0;

begin

    cur_st : PROCESS(Clk_i, Reset_i)
    begin
        if Reset_i = '1' then
            Current_state <= Zero;
        elsif rising_edge(Clk_i) then
            Current_state <= Next_state;
        end if;
    end process;

    next_st : PROCESS(Current_state, Convert_i, N_s)
    begin
        case Current_state is
            when Zero =>
                if Convert_i = '1' then
                    Next_state  <= Disconnect_1;
                else
                    Next_state  <= Zero;
                end if;

            when Disconnect_1 =>
                if N_s = 8 then
                    Next_state  <= Compute;
                else
                    Next_state  <= Sample;
                end if;

            when Sample =>
                Next_state      <= Disconnect_2;

            when Disconnect_2 =>
                Next_state      <= Compute;

            when Compute =>
                Next_state      <= Disconnect_1;

            when Update =>
                Next_state      <= Next_Byte;

            when Next_Byte =>
                Next_state      <= Zero

            when others =>
                Next_state      <= Zero;

        end case;
    end process;


    decode : PROCESS(Current_state, Data_i, N_s)
    begin
        -- Default output --
        S1_o         <= '0';
        S2n_o        <= '1';
        S3n_o        <= '1';
        S4_o         <= '0';
        Busy_o       <= '1';
        New_data_o   <= '0';
        inc_cnt_s    <= '0';

        case(Current_state) is
            when Zero =>
                S2n_o       <= '0';
                S3n_o       <= '0';
                Busy_o      <= '0';

            when Disconnect_1 => -- Default
            when Disconnect_2 => -- Default

            when Sample =>
                if Data_i[N_s] = '1' then
                    S1_o    <= '1';
                else
                    S1_o    <= '0';

                Busy_o      <= '1';

            when Compute =>
                S3n_o       <= '0';
                inc_cnt_s   <= '1';
                Busy_o      <= '1';

            when Update =>
                S4_o        <= '1';
                Busy_o      <= '1';

            when Next_Byte =>
                New_data_o  <= '1';
                inc_cnt_s   <= '1';

        end case;
    end process;


    counter : PROCESS(Clk_i, Reset_i)
    begin
        if Reset_i = '1' then
            N_s <= 0;
        elsif rising_edge(Clk_i) then

            if inc_cnt_s = '1' then
                N_s <= N_s + 1;
            elsif N_s > 8 then
                N_s = 0;
            end if;
        end if;
    end process;


end Behavior;