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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 01/24/2020 12:17:40 AM
  7. // Design Name:
  8. // Module Name: FullAdder
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21.  
  22. // Test Syntax
  23. /*
  24. module FullAdder(
  25.     a,
  26.     b,
  27.     cin,
  28.     o_sum,
  29.     o_carry
  30.     );
  31.     input a,b,cin;
  32.     output reg o_sum, o_carry;
  33.    
  34.     reg temp1;
  35.     reg temp2;
  36.     reg temp3;
  37.    
  38.     always @(a or b or cin) begin
  39.         assign temp1 = a ^ b;
  40.         assign temp2 = ( a ^ b ) & cin;
  41.         assign temp3 = a & b;
  42.     end
  43.    
  44.     always @ (temp1 or temp2 or temp3 or cin) begin
  45.         assign o_sum = temp1 ^ cin;
  46.         assign o_carry = temp2 | temp3;        
  47.     end
  48.    
  49. endmodule
  50. */
  51. module FullAdder(cout, s, a, b, cin);
  52.     output cout;
  53.     output s;
  54.     input a;
  55.     input b;
  56.     input cin;
  57.     reg cout, s;
  58.     always @(a, b, cin ) begin
  59.         assign s = ( a ^ b ) ^ cin;
  60.         assign cout = ((a ^ b) & cin) | ( a & b);
  61.     end
  62. endmodule
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