`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/24/2020 12:17:40 AM
// Design Name:
// Module Name: FullAdder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

// Test Syntax
/*
module FullAdder(
    a,
    b,
    cin,
    o_sum,
    o_carry
    );
    input a,b,cin;
    output reg o_sum, o_carry;

    reg temp1;
    reg temp2;
    reg temp3;

    always @(a or b or cin) begin
        assign temp1 = a ^ b;
        assign temp2 = ( a ^ b ) & cin;
        assign temp3 = a & b;
    end

    always @ (temp1 or temp2 or temp3 or cin) begin
        assign o_sum = temp1 ^ cin;
        assign o_carry = temp2 | temp3;
    end

endmodule
*/
module FullAdder(cout, s, a, b, cin);
    output cout;
    output s;
    input a;
    input b;
    input cin;
    reg cout, s;
    always @(a, b, cin ) begin
        assign s = ( a ^ b ) ^ cin;
        assign cout = ((a ^ b) & cin) | ( a & b);
    end
endmodule