shader: MESA_SHADER_FRAGMENT
name: GLSL3
inputs: 0
outputs: 1
uniforms: 0
shared: 0
decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 0, 0)
decl_function main (0 params)

impl main {
	decl_reg vec1 32 r0
	decl_reg vec1 32 r1
	decl_reg vec1 32 r2
	block block_0:
	/* preds: */
	vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */)
	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
	vec1 32 ssa_2 = load_const (0x3f800000 /* 1.000000 */)
	vec1 32 ssa_3 = load_const (0xbf800000 /* -1.000000 */)
	vec4 32 ssa_4 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */)
	r1 = mov ssa_2
	r0 = mov ssa_0
	/* succs: block_1 */
	loop {
		block block_1:
		/* preds: block_0 block_4 */
		vec1 32 ssa_7 = sge r0, ssa_2
		vec1 32 ssa_8 = sge ssa_3, r0
		vec1 32 ssa_9 = fcsel ssa_7, ssa_1, ssa_8
		intrinsic discard_if (ssa_9) ()
		/* succs: block_2 block_3 */
		if ssa_7 {
			block block_2:
			/* preds: block_1 */
			break
			/* succs: block_5 */
		} else {
			block block_3:
			/* preds: block_1 */
			/* succs: block_4 */
		}
		block block_4:
		/* preds: block_3 */
		r2 = fadd r1, ssa_2
		r0 = mov r1
		r1 = mov r2
		/* succs: block_1 */
	}
	block block_5:
	/* preds: block_2 */
	intrinsic store_output (ssa_4, ssa_0) (0, 15, 0, 160) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* type=float32 */	/* gl_FragColor */
	/* succs: block_6 */
	block block_6:
}

ppir_node_add_dep: succ: 0xaaab0d4cb180, pred: 0xaaab0d4ab510, dep: 0xaaab0d4b9350
ppir_node_add_dep: succ: 0xaaab0d4cab90, pred: 0xaaab0d4b2750, dep: 0xaaab0d4b09d0
ppir_node_add_dep: succ: 0xaaab0d4ca8f0, pred: 0xaaab0d4b4300, dep: 0xaaab0d4ba490
ppir_node_add_dep: succ: 0xaaab0d4ace80, pred: 0xaaab0d4b30c0, dep: 0xaaab0d458e80
num inputs: 3
ppir_node_add_dep: succ: 0xaaab0d4c1bc0, pred: 0xaaab0d4ca8f0, dep: 0xaaab0d4b1c30
ppir_node_add_dep: succ: 0xaaab0d4c1bc0, pred: 0xaaab0d4ae120, dep: 0xaaab0d4bbbc0
ppir_node_add_dep: succ: 0xaaab0d4c1bc0, pred: 0xaaab0d4ace80, dep: 0xaaab0d459e00
ppir_node_add_dep: succ: 0xaaab0d4c90e0, pred: 0xaaab0d4c1bc0, dep: 0xaaab0d4ada80
ppir_emit_discard_if: 0
ppir_node_add_dep: succ: 0xaaab0d4c92b0, pred: 0xaaab0d4ca8f0, dep: 0xaaab0d4b7d30
ppir_node_add_dep: succ: 0xaaab0d4c6d40, pred: 0xaaab0d496770, dep: 0xaaab0d4c67e0
ppir_node_add_dep: succ: 0xaaab0d4af080, pred: 0xaaab0d4c6d40, dep: 0xaaab0d47e840
ppir_node_add_dep: succ: 0xaaab0d4c7af0, pred: 0xaaab0d497490, dep: 0xaaab0d4b8170
ppir_node_add_dep: succ: 0xaaab0d4c92b0, pred: 0xaaab0d4c90e0, dep: 0xaaab0d4cab10
ppir_node_add_dep: succ: 0xaaab0d4c6af0, pred: 0xaaab0d4af080, dep: 0xaaab0d4b4470
========prog========
-------block 0000 ------
const 1 ssa1 dest: ssa 0xaaab0d4ab4a8
const 3 ssa3 dest: ssa 0xaaab0d4c9248
const 4 ssa4 dest: ssa 0xaaab0d4b73c8
mov 5 reg1 dest: reg    1 src: ssa 0xaaab0d4ab598
  const 2 ssa2 dest: ssa 0xaaab0d4ab598
mov 6 reg0 dest: reg    0 src: ssa 0xaaab0d4b27d8
  const 0 ssa0 dest: ssa 0xaaab0d4b27d8
-------block 0001 ------
branch 15 new src: ssa 0xaaab0d4ca960
  ge 7 ssa7 dest: ssa 0xaaab0d4ca960 src: reg    0 src: ssa 0xaaab0d4b4388
    const 8 new dest: ssa 0xaaab0d4b4388
  branch 14 new src: ssa 0xaaab0d4c1c30
    select 11 ssa9 dest: ssa 0xaaab0d4c1c30 src: ssa 0xaaab0d4ca960 src: ssa 0xaaab0d4ae1a8 src: ssa 0xaaab0d4acef0
      +ge 7 ssa7 dest: ssa 0xaaab0d4ca960 src: reg    0 src: ssa 0xaaab0d4b4388
      const 12 new dest: ssa 0xaaab0d4ae1a8
      ge 9 ssa8 dest: ssa 0xaaab0d4acef0 src: ssa 0xaaab0d4b3148 src: reg    0
        const 10 new dest: ssa 0xaaab0d4b3148
-------block 0002 ------
branch 16 new
-------block 0004 ------
mov 19 reg0 dest: reg    0 src: reg    1
branch 21 new
  mov 20 reg1 dest: reg    1 src: reg    2
    add 17 reg2 dest: reg    2 src: reg    1 src: ssa 0xaaab0d4967f8
      const 18 new dest: ssa 0xaaab0d4967f8
-------block 0005 ------
st_col 22 new src: ssa 0xaaab0d497518
  const 23 new dest: ssa 0xaaab0d497518
-------block 0000 ------
discard 13 new
====================
ppir_lower_const: node: 0xaaab0d4b2750, ssa: 0xaaab0d4b27d8
ppir_lower_const: node: 0xaaab0d4ab510, ssa: 0xaaab0d4ab598
ppir_lower_const: node: 0xaaab0d4b4300, ssa: 0xaaab0d4b4388
ppir_lower_const: node: 0xaaab0d4b30c0, ssa: 0xaaab0d4b3148
ppir_lower_const: node: 0xaaab0d4ae120, ssa: 0xaaab0d4ae1a8
ppir_node_add_dep: succ: 0xaaab0d4bc730, pred: 0xaaab0d4ca8f0, dep: 0xaaab0d4c7e90
ppir_node_add_dep: succ: 0xaaab0d4c90e0, pred: 0xaaab0d4b7340, dep: 0xaaab0d4c5b50
ppir_node_add_dep: succ: 0xaaab0d4c92b0, pred: 0xaaab0d4c91c0, dep: 0xaaab0d4b4560
ppir_lower_const: node: 0xaaab0d496770, ssa: 0xaaab0d4967f8
ppir_lower_const: node: 0xaaab0d497490, ssa: 0xaaab0d497518
ppir: lower const create move 27 for 23
ppir_node_add_dep: succ: 0xaaab0d4af250, pred: 0xaaab0d497490, dep: 0xaaab0d4c7730
========prog========
-------block 0000 ------
mov 5 reg1 dest: reg    1 src: ssa 0xaaab0d4ab598
  const 2 ssa2 dest: ssa 0xaaab0d4ab598
mov 6 reg0 dest: reg    0 src: ssa 0xaaab0d4b27d8
  const 0 ssa0 dest: ssa 0xaaab0d4b27d8
-------block 0001 ------
branch 15 new src: ssa 0xaaab0d4ca960 src: ssa 0xaaab0d4c9248
  ge 7 ssa7 dest: ssa 0xaaab0d4ca960 src: reg    0 src: ssa 0xaaab0d4b4388
    const 8 new dest: ssa 0xaaab0d4b4388
  branch 14 new src: ssa 0xaaab0d4c1c30 src: ssa 0xaaab0d4b73c8
    select 11 ssa9 dest: ssa 0xaaab0d4c1c30 src: ssa 0xaaab0d4ca960 src: ssa 0xaaab0d4ae1a8 src: ssa 0xaaab0d4acef0
      mov 24 new dest: ssa 0xaaab0d4bc7a0 src: ssa 0xaaab0d4bc7a0
        +ge 7 ssa7 dest: ssa 0xaaab0d4ca960 src: reg    0 src: ssa 0xaaab0d4b4388
      const 12 new dest: ssa 0xaaab0d4ae1a8
      ge 9 ssa8 dest: ssa 0xaaab0d4acef0 src: ssa 0xaaab0d4b3148 src: reg    0
        const 10 new dest: ssa 0xaaab0d4b3148
    const 25 new dest: ssa 0xaaab0d4b73c8
  const 26 new dest: ssa 0xaaab0d4c9248
-------block 0002 ------
branch 16 new
-------block 0004 ------
mov 19 reg0 dest: reg    0 src: reg    1
branch 21 new
  mov 20 reg1 dest: reg    1 src: reg    2
    add 17 reg2 dest: reg    2 src: reg    1 src: ssa 0xaaab0d4967f8
      const 18 new dest: ssa 0xaaab0d4967f8
-------block 0005 ------
st_col 22 new src: ssa 0xaaab0d4af2c0
  mov 27 new dest: ssa 0xaaab0d4af2c0 src: ssa 0xaaab0d497518
    const 23 new dest: ssa 0xaaab0d497518
-------block 0000 ------
discard 13 new
====================
ppir_do_node_to_instr: const: 0xaaab0d4ab510
ppir_do_node_to_instr: const: 0xaaab0d4b2750
ppir_do_node_to_instr: const: 0xaaab0d4b4300
ppir_do_node_to_instr: const: 0xaaab0d4ae120
ppir_do_node_to_instr: const: 0xaaab0d4b30c0
ppir_do_node_to_instr: const: 0xaaab0d4b7340
ppir_do_node_to_instr: const: 0xaaab0d4c91c0
ppir_do_node_to_instr: const: 0xaaab0d496770
ppir: node_to_instr create move 28 from store 22
ppir_node_remove_dep: dep: 0xaaab0d4b8170
ppir_node_add_dep: succ: 0xaaab0d4c4e20, pred: 0xaaab0d4af250, dep: 0xaaab0d4c77a0
ppir_node_add_dep: succ: 0xaaab0d4c7af0, pred: 0xaaab0d4c4e20, dep: 0xaaab0d4b0590
ppir_do_node_to_instr: const: 0xaaab0d497490
======ppir instr list======
      vary texl unif vmul smul vadd sadd comb stor brch const0|1
 000: null null null null null null 5    null null null 1.000000 |
 001: null null null null null null 6    null null null 0.000000 |
------------------------
 002: null null null null null null null null null 15   0.000000 |
 003: null null null null null null null null null 14   0.000000 |
 004: null null null null 24   null 11   null null null 0.000000 |
 005: null null null null 7    null null null null null 1.000000 |
 006: null null null null 9    null null null null null -1.000000 |
------------------------
 007: null null null null null null null null null 16   |
------------------------
 008: null null null null null null 19   null null null |
 009: null null null null null null null null null 21   |
 010: null null null null null null 20   null null null |
 011: null null null null null null 17   null null null 1.000000 |
------------------------
*012: null null null 27   null 28   null null null null 0.000000 1.000000 |
------------------------
*013: null null null null null null null null null 13   |
------------------------
======ppir instr depend======
[0]
[1]
------------------------
[2[5][3[4[5][6]]]]
------------------------
[7]
------------------------
[8]
[9[10[11]]]
------------------------
[12]
------------------------
[13]
------------------------
liveness:
reg/ssa0 (0xaaab0d4ad6c0) in: 0, out: 2147483647, idx: 0
reg/ssa1 (0xaaab0d4adca0) in: 0, out: 2147483647, idx: 1
reg/ssa2 (0xaaab0d4a9f30) in: 0, out: 2147483647, idx: 2
reg/ssa3 (0xaaab0d4ca960) in: 2, out: 6, idx: 0
reg/ssa4 (0xaaab0d4acef0) in: 3, out: 4, idx: 0
reg/ssa5 (0xaaab0d4c1c30) in: 4, out: 5, idx: 0
reg/ssa6 (0xaaab0d4c4e90) in: 12, out: 2147483647, idx: 0
ppir_regalloc_prog_try: reg 0 conflicts with 1
ppir_regalloc_prog_try: reg 0 conflicts with 2
ppir_regalloc_prog_try: reg 0 conflicts with 3
ppir_regalloc_prog_try: reg 0 conflicts with 4
ppir_regalloc_prog_try: reg 0 conflicts with 5
ppir_regalloc_prog_try: reg 0 conflicts with 6
ppir_regalloc_prog_try: reg 1 conflicts with 2
ppir_regalloc_prog_try: reg 1 conflicts with 3
ppir_regalloc_prog_try: reg 1 conflicts with 4
ppir_regalloc_prog_try: reg 1 conflicts with 5
ppir_regalloc_prog_try: reg 1 conflicts with 6
ppir_regalloc_prog_try: reg 2 conflicts with 3
ppir_regalloc_prog_try: reg 2 conflicts with 4
ppir_regalloc_prog_try: reg 2 conflicts with 5
ppir_regalloc_prog_try: reg 2 conflicts with 6
ppir_regalloc_prog_try: reg 3 conflicts with 4
ppir_regalloc_prog_try: reg 3 conflicts with 5
ppir_regalloc_prog_try: reg 4 conflicts with 5
======ppir regalloc result======
000: (idx: 5 | dreg: 5 | sreg: 48)
001: (idx: 6 | dreg: 4 | sreg: 48)
005: (idx: 7 | dreg: 0 | sreg: 4 sreg: 48)
006: (idx: 9 | dreg: 1 | sreg: 48 sreg: 4)
004: (idx: 24 | dreg: 68 | sreg: 0) (idx: 11 | dreg: 2 | sreg: 0 sreg: 48 sreg: 1)
003: (idx: 14 |  | sreg: 2 sreg: 48)
002: (idx: 15 |  | sreg: 0 sreg: 48)
007: (idx: 16 |  | )
008: (idx: 19 | dreg: 4 | sreg: 5)
011: (idx: 17 | dreg: 6 | sreg: 5 sreg: 48)
010: (idx: 20 | dreg: 5 | sreg: 6)
009: (idx: 21 |  | )
012: (idx: 27 | dreg: 64 | sreg: 48) (idx: 28 | dreg: 0 | sreg: 64)
013: (idx: 13 |  | )
--------------------------
liveness:
reg/ssa0 (0xaaab0d4ad6c0) in: 0, out: 2147483647, idx: 4
reg/ssa1 (0xaaab0d4adca0) in: 0, out: 2147483647, idx: 5
reg/ssa2 (0xaaab0d4a9f30) in: 0, out: 2147483647, idx: 6
reg/ssa3 (0xaaab0d4ca960) in: 2, out: 6, idx: 0
reg/ssa4 (0xaaab0d4acef0) in: 3, out: 4, idx: 1
reg/ssa5 (0xaaab0d4c1c30) in: 4, out: 5, idx: 2
reg/ssa6 (0xaaab0d4c4e90) in: 12, out: 2147483647, idx: 0
========ppir codegen========
000 (@     0): 02222004 3e450030 00001e00 00000000
mov.sacc $1.y ^const0.x, const0 1.000000 0.000000 0.000000 0.000000
001 (@     4): 02222004 3e440030 00000000 00000000
mov.sacc $1.x ^const0.x, const0 0.000000 0.000000 0.000000 0.000000
005 (@     8): 02220804 1c403004 00000f00 00000000
ge.smul $0.x $1.x ^const0.x, const0 1.000000 0.000000 0.000000 0.000000
006 (@    12): 022a0804 1c410430 00002f00 00000000
ge.smul $0.y ^const0.x $1.x, const0 -1.000000 0.000000 0.000000 0.000000
004 (@    16): 02322805 3e000000 0b90804c 00000000 00000000
mov.smul $0.x, sel.sacc $0.z ^const0.x $0.y, const0 0.000000 0.000000 0.000000 0.000000
003 (@    21): 02330006 00050b00 00004400 00000030 00000000 00000000
branch.ne $0.z ^const0.x 55, const0 0.000000 0.000000 0.000000 0.000000
002 (@    27): 02230006 00020300 00001400 00000030 00000000 00000000
branch.eq $0.x ^const0.x 37, const0 0.000000 0.000000 0.000000 0.000000
007 (@    33): 02110004 00070000 00002000 00000030
branch 49
008 (@    37): 02202002 3e440005
mov.sacc $1.x $1.y
011 (@    39): 02122004 00463005 00001e00 00000000
add.sacc $1.z $1.y ^const0.x, const0 1.000000 0.000000 0.000000 0.000000
010 (@    43): 02202002 3e450006
mov.sacc $1.y $1.z
009 (@    45): 02310004 00070000 ffffb600 0000003f
branch 8
012 (@    49): 02221426 0000004c 007207c0 007e7800 001e0000 00000000
mov.vmul ^const0.xyxx , mov.vacc $0 ^vmul, const0 0.000000 1.000000 0.000000 0.000000, stop
013 (@    55): 00010024 007f0003 00000000 00000000
discard, stop
-----------------------
Probe color at (0,0)
  Expected: 0.000000 1.000000 0.000000 0.000000
  Observed: 0.000000 0.000000 0.000000 0.000000
Test failure on line 26
PIGLIT: {"result": "fail" }