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- --Lab #2: Top (Dean Nguyen)--
- --Libraries--
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
- USE IEEE.NUMERIC_STD.ALL;
- --Entity--
- ENTITY Top IS
- GENERIC ( SIZE : INTEGER := 10);
- PORT ( CLK, RESET_N, LOAD : IN STD_LOGIC; --Clock, reset, load, serial_in from XOR
- INPUT : IN STD_LOGIC_VECTOR(9 DOWNTO 0); --Random seed input
- OUTPUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); --Output
- END Top;
- --Architecture--
- ARCHITECTURE structural OF Top IS
- --Components--
- COMPONENT Shift_Reg
- GENERIC ( SIZE : INTEGER := 10); --Generic with default value
- PORT ( CLK, RESET_N, LOAD, SERIAL_IN : IN STD_LOGIC; --Clock, reset, load, serial_in from XOR
- SEED : IN STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Random seed input
- PARALLEL_OUT : OUT STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0)); --Output
- END COMPONENT;
- COMPONENT XOR_Gate
- GENERIC ( SIZE : INTEGER := 2); --Generic with default value
- PORT ( INPUT : IN STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Input by # of inputs
- OUTPUT : OUT STD_LOGIC); --Output
- END COMPONENT;
- --Signals--
- SIGNAL SHIFT_REG_INPUT : STD_LOGIC; --Input signal to serial_In from XOR output
- SIGNAL SHIFT_REG_OUTPUT : STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Output signal from parallel_Out
- SIGNAL XOR_INPUT : STD_LOGIC_VECTOR((SIZE - 8) - 1 DOWNTO 0); --Input signal from parallel_out to XOR input
- BEGIN
- --Mapping--
- uut: Shift_Reg
- GENERIC MAP (
- SIZE => 10)
- PORT MAP (
- CLK => CLK,
- RESET_N => RESET_N,
- LOAD => LOAD,
- SERIAL_IN => SHIFT_REG_INPUT,
- SEED => INPUT,
- PARALLEL_OUT => SHIFT_REG_OUTPUT);
- uut1: XOR_Gate
- GENERIC MAP (
- SIZE => 2)
- PORT MAP (
- INPUT => XOR_INPUT,
- OUTPUT => SHIFT_REG_INPUT);
- --Structure--
- XOR_INPUT <= SHIFT_REG_OUTPUT(9) & SHIFT_REG_OUTPUT(6); --Concatenating the two bits (9, 6)
- OUTPUT <= SHIFT_REG_OUTPUT; --Shows output
- END structural;
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