Advertisement
Guest User

Untitled

a guest
Oct 15th, 2019
132
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 7.77 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use ieee.numeric_std.all;
  4.  
  5. entity Voltmeter is
  6. Port ( clk : in STD_LOGIC;
  7. reset : in STD_LOGIC;
  8. MUXSELECT : in STD_LOGIC;
  9. LEDR : out STD_LOGIC_VECTOR (9 downto 0);
  10. HEX0,HEX1,HEX2,HEX3,HEX4,HEX5 : out STD_LOGIC_VECTOR (7 downto 0)
  11. );
  12.  
  13. end Voltmeter;
  14.  
  15. architecture Behavioral of Voltmeter is
  16.  
  17. Signal A, Num_Hex0, Num_Hex1, Num_Hex2, Num_Hex3, Num_Hex4, Num_Hex5 : STD_LOGIC_VECTOR (3 downto 0):= (others=>'0');
  18. Signal DP_in: STD_LOGIC_VECTOR (5 downto 0);
  19. Signal ADC_read,rsp_data,q_outputs_1,q_outputs_2 : STD_LOGIC_VECTOR (11 downto 0);
  20. Signal voltage: STD_LOGIC_VECTOR (12 downto 0);
  21. Signal busy: STD_LOGIC;
  22. signal response_valid_out_i1,response_valid_out_i2,response_valid_out_i3 : STD_LOGIC_VECTOR(0 downto 0);
  23. Signal bcd: STD_LOGIC_VECTOR(15 DOWNTO 0);
  24. Signal Q_temp1 : std_logic_vector(11 downto 0);
  25. Signal MUXOUT : std_logic_vector (12 downto 0);
  26. Signal distance_signal: STD_LOGIC_VECTOR(12 DOWNTO 0);
  27.  
  28. component Mux is -- declare the component
  29. Port ( input1 : in STD_LOGIC_VECTOR (12 downto 0);
  30. input2 : in STD_LOGIC_VECTOR (12 downto 0);
  31. S : in STD_LOGIC;
  32. MUXOUT : out STD_LOGIC_VECTOR (12 downto 0)
  33. );
  34. End Component;
  35.  
  36.  
  37. Component SevenSegment is
  38. Port( Num_Hex0,Num_Hex1,Num_Hex2,Num_Hex3,Num_Hex4,Num_Hex5 : in STD_LOGIC_VECTOR (3 downto 0);
  39. Hex0,Hex1,Hex2,Hex3,Hex4,Hex5 : out STD_LOGIC_VECTOR (7 downto 0);
  40. DP_in : in STD_LOGIC_VECTOR (5 downto 0)
  41. );
  42. End Component ;
  43.  
  44. Component ADC_Conversion is
  45. Port( MAX10_CLK1_50 : in STD_LOGIC;
  46. response_valid_out : out STD_LOGIC;
  47. ADC_out : out STD_LOGIC_VECTOR (11 downto 0)
  48. );
  49. End Component ;
  50.  
  51. Component binary_bcd IS
  52. PORT(
  53. clk : IN STD_LOGIC; --system clock
  54. reset : IN STD_LOGIC; --active low asynchronus reset
  55. ena : IN STD_LOGIC; --latches in new binary number and starts conversion
  56. binary : IN STD_LOGIC_VECTOR(12 DOWNTO 0); --binary number to convert
  57. busy : OUT STD_LOGIC; --indicates conversion in progress
  58. bcd : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --resulting BCD number
  59. );
  60. END Component;
  61.  
  62. Component registers is
  63. generic(bits : integer);
  64. port
  65. (
  66. clk : in std_logic;
  67. reset : in std_logic;
  68. enable : in std_logic;
  69. d_inputs : in std_logic_vector(bits-1 downto 0);
  70. q_outputs : out std_logic_vector(bits-1 downto 0)
  71. );
  72. END Component;
  73.  
  74. Component averager is
  75. port(
  76. clk, reset : in std_logic;
  77. Din : in std_logic_vector(11 downto 0);
  78. EN : in std_logic; -- response_valid_out
  79. Q : out std_logic_vector(11 downto 0)
  80. );
  81. end Component;
  82.  
  83. component voltage2distance
  84. PORT(
  85. clk : IN STD_LOGIC;
  86. reset : IN STD_LOGIC;
  87. voltage : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
  88. distance : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
  89. );
  90. END Component;
  91.  
  92. begin
  93. Num_Hex0 <= bcd(3 downto 0);
  94. Num_Hex1 <= bcd(7 downto 4);
  95. Num_Hex2 <= bcd(11 downto 8);
  96. -- Num_Hex4 <= "1111";
  97. -- Num_Hex5 <= "1111";
  98. with bcd (15 downto 12) select
  99. Num_Hex3 <= "1111" when "0000",
  100. bcd(15 downto 12) when others;
  101. Num_Hex4 <= bcd(3 downto 0) when (unsigned(distance_signal) = 3333) else "1111";
  102. Num_Hex5 <= bcd(3 downto 0) when (unsigned(distance_signal) = 3333) else "1111";
  103. --DP_in <= "001000";-- position of the decimal point in the display
  104.  
  105. with MUXSELECT select
  106. DP_in <= "000100" when '0',
  107. "001000" when '1',
  108. "000000" when others;
  109.  
  110.  
  111.  
  112.  
  113. ave : averager
  114. port map(
  115. clk => clk,
  116. reset => reset,
  117. Din => q_outputs_2,
  118. EN => response_valid_out_i3(0),
  119. Q => Q_temp1
  120. );
  121.  
  122. sync1 : registers
  123. generic map(bits => 12)
  124. port map(
  125. clk => clk,
  126. reset => reset,
  127. enable => '1',
  128. d_inputs => ADC_read,
  129. q_outputs => q_outputs_1
  130. );
  131.  
  132. sync2 : registers
  133. generic map(bits => 12)
  134. port map(
  135. clk => clk,
  136. reset => reset,
  137. enable => '1',
  138. d_inputs => q_outputs_1,
  139. q_outputs => q_outputs_2
  140. );
  141.  
  142. sync3 : registers
  143. generic map(bits => 1)
  144. port map(
  145. clk => clk,
  146. reset => reset,
  147. enable => '1',
  148. d_inputs => response_valid_out_i1,
  149. q_outputs => response_valid_out_i2
  150. );
  151.  
  152. sync4 : registers
  153. generic map(bits => 1)
  154. port map(
  155. clk => clk,
  156. reset => reset,
  157. enable => '1',
  158. d_inputs => response_valid_out_i2,
  159. q_outputs => response_valid_out_i3
  160. );
  161.  
  162. SevenSegment_ins: SevenSegment
  163. PORT MAP( Num_Hex0 => Num_Hex0,
  164. Num_Hex1 => Num_Hex1,
  165. Num_Hex2 => Num_Hex2,
  166. Num_Hex3 => Num_Hex3,
  167. Num_Hex4 => Num_Hex4,
  168. Num_Hex5 => Num_Hex5,
  169. Hex0 => Hex0,
  170. Hex1 => Hex1,
  171. Hex2 => Hex2,
  172. Hex3 => Hex3,
  173. Hex4 => Hex4,
  174. Hex5 => Hex5,
  175. DP_in => DP_in
  176. );
  177.  
  178. ADC_Conversion_ins: ADC_Conversion PORT MAP(
  179. MAX10_CLK1_50 => clk,
  180. response_valid_out => response_valid_out_i1(0),
  181. ADC_out => ADC_read);
  182.  
  183. voltage2distance_ins: voltage2distance PORT MAP(
  184. clk => clk,
  185. reset => reset,
  186. voltage => voltage,
  187. distance => distance_signal
  188. );
  189.  
  190. mux_ins : Mux PORT MAP (
  191. input1 => distance_signal,
  192. input2 => voltage,
  193. S => MUXSELECT,
  194. MUXOUT => MUXOUT
  195. );
  196.  
  197. LEDR(9 downto 0) <=Q_temp1(11 downto 2); -- gives visual display of upper binary bits to the LEDs on board
  198.  
  199. -- in line below, can change the scaling factor (i.e. 2500), to calibrate the voltage reading to a reference voltmeter
  200. voltage <= std_logic_vector(resize(unsigned(Q_temp1)*2500*2/4096,voltage'length)); -- Converting ADC_read a 12 bit binary to voltage readable numbers
  201.  
  202.  
  203.  
  204. binary_bcd_ins: binary_bcd
  205. PORT MAP(
  206. clk => clk,
  207. reset => reset,
  208. ena => '1',
  209. binary => MUXOUT,
  210. busy => busy,
  211. bcd => bcd
  212. );
  213. end Behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement