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- match opcode & 0xF000 {
- // match against nibbles &'d with 0xF
- 0x0000 => match opcode & 0x00FF {
- 0x00E0 => {
- // CLS - Clear display
- self.display.clear();
- }
- 0x00EE => {
- // RET
- self.pc = self.stack[self.sp as usize];
- self.sp -= 1;
- print!("Opcode: [{:>04X}] ", opcode);
- }
- _ => {
- // 0nnn - SYS addr, no longer used
- print!("Opcode: [{:>04X}] ", opcode);
- }
- },
- 0x1000 => {
- // 1nnn - JP addr
- self.pc = opcode & 0x0FFF;
- }
- 0x2000 => {
- // 2nnn - CALL addr
- self.sp += 1;
- self.stack[self.sp as usize] = self.pc;
- self.pc = opcode & 0x0FFF;
- }
- 0x3000 => {
- // 3xkk - SE Vx, byte
- if u16::from(self.v[(opcode & 0x0F00) as usize]) == opcode & 0x00FF {
- self.pc += 2;
- }
- }
- 0x4000 => {
- // 4xkk - SNE Vx, byte
- if u16::from(self.v[(opcode & 0x0F00) as usize]) != opcode & 0x00FF {
- self.pc += 2;
- }
- }
- 0x5000 => {
- // 5xy0 - SE Vx, Vy
- if self.v[(opcode & 0x0F00) as usize] == self.v[(opcode & 0x00F0) as usize] {
- self.pc += 2;
- }
- }
- 0x6000 => {
- // 6xkk - LD Vx, byte
- self.v[(opcode & 0x0F00) as usize] = (opcode & 0x00FF) as u8;
- }
- 0x7000 => {
- // 7xkk - ADD Vx, byte
- self.v[(opcode & 0x0F00) as usize] += (opcode & 0x00FF) as u8;
- }
- 0x8000 => match opcode & 0x000F {
- // bitwise operations
- 0x0000 => {
- // 8xy0 - LD Vx, Vy
- self.v[(opcode & 0x0F00) as usize] = self.v[(opcode & 0x00F0) as usize];
- }
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