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a guest Apr 18th, 2019 74 Never
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  1. module mux2_1_flux_date(input a,b,input sel,output o);assign o = sel ? b : a;endmodulemodule mux2_1_comp(input a,b,input sel,output reg o);always@(a,b,sel)begino = a;if(sel)o = b;elseo = a;endendmodule
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