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- ; This program reads the analogue input
- ; voltage on the ADC and displays it on
- ; the scope via the DAC.
- ; A sample is taken from the ADC every 20 us
- ; This is achieved by setting timer 0
- ; to interrupt the main program every 20 us.
- ; The timer 0 ISR then initiates an ADC
- ; conversion.
- ; When the conversion is complete the
- ; ADC interrupt line goes low. This line
- ; is interfaced with the 8051 external 0
- ; interrupt line. The external 0 ISR
- ; therefore takes the reading from the ADC
- ; on P2 and passes it to the DAC on P1.
- ; Therefore, while the program is running,
- ; the scope voltage level should be the
- ; same as the ADC input voltage.
- ; However, when a change is made to the
- ; ADC input voltage it will take some time
- ; for the scope to update (ie; until the
- ; next timer 0 interrupt). This simulates
- ; the 20 us delay between samples.
- ; Note: when running this program make sure
- ; the ADC is enabled (the blue button above
- ; the input voltage slider should say ADC Enabled).
- org 0 ; reset vector
- jmp main ; jump to the main program
- org 3 ; external 0 interrupt vector
- jmp ext0ISR ; jump to the external 0 ISR
- org 0bh ; timer 0 interrupt vector
- jmp timer0ISR ; jump to timer 0 ISR
- org 30h ; main program starts here
- main:
- setb it0 ; set external 0 interrupt as edge-activated
- setb ex0 ; enable external 0 interrupt
- clr p0.7 ; enable DAC WR line
- mov tmod, #2 ; set timer 0 as 8-bit auto-reload interval timer
- mov th0, #-20 ; put -20 into timer 0 high-byte - this reload value,
- ; with system clock of 12 MHz, will result in a timer 0 overflow every 20 us
- mov tl0, #-20 ; put the same value in the low byte to ensure the timer starts counting from
- ; 236 (256 - 20) rather than 0
- setb tr0 ; start timer 0
- setb et0 ; enable timer 0 interrupt
- setb ea ; set the global interrupt enable bit
- jmp $ ; jump back to the same line (ie; do nothing)
- ; end of main program
- ; timer 0 ISR - simply starts an ADC conversion
- timer0ISR:
- clr p3.6 ; clear ADC WR line
- setb p3.6 ; then set it - this results in the required positive edge to start a conversion
- reti ; return from interrupt
- ; external 0 ISR - responds to the ADC conversion complete interrupt
- ext0ISR:
- clr p3.7 ; clear the ADC RD line - this enables the data lines
- mov p1, p2 ; take the data from the ADC on P2 and send it to the DAC data lines on P1
- setb p3.7 ; disable the ADC data lines by setting RD
- reti ; return from interrupt
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