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Dec 2nd, 2021
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  1. LIBRARY IEEE;
  2. USE IEEE.STD_LOGIC_1164.ALL;
  3. USE IEEE.numeric_std.ALL;
  4.  
  5.  
  6. ENTITY pe IS
  7.  
  8.     GENERIC (data_width : INTEGER := 8);
  9.  
  10.     PORT (
  11.         numberin : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
  12.         numberout, number : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
  13.         eni, reset, clk : IN STD_LOGIC;
  14.         eno : OUT STD_LOGIC
  15.     );
  16.  
  17. END pe;
  18.  
  19. ARCHITECTURE behavior OF pe IS
  20.  
  21.     SIGNAL stored : STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0) := "00000000";
  22.  
  23. BEGIN
  24.  
  25.     PROCESS (clk, reset, eni, numberin)
  26.     BEGIN
  27.  
  28.         IF rising_edge (clk) THEN
  29.             IF eni = '1' THEN
  30.                 IF numberin > stored THEN
  31.                     eno <= '1';
  32.                     numberout <= stored;
  33.                     stored <= numberin;
  34.                 ELSE
  35.                     eno <= '1';
  36.                     numberout <= numberin;
  37.                 END IF;
  38.             END IF;
  39.         END IF;
  40.     END PROCESS;
  41.  
  42. END behavior;
  43.  
  44.  
  45.  
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