LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;


ENTITY pe IS

    GENERIC (data_width : INTEGER := 8);

    PORT (
        numberin : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
        numberout, number : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
        eni, reset, clk : IN STD_LOGIC;
        eno : OUT STD_LOGIC
    );

END pe;

ARCHITECTURE behavior OF pe IS

    SIGNAL stored : STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0) := "00000000";

BEGIN

    PROCESS (clk, reset, eni, numberin)
    BEGIN

        IF rising_edge (clk) THEN
            IF eni = '1' THEN
                IF numberin > stored THEN
                    eno <= '1';
                    numberout <= stored;
                    stored <= numberin;
                ELSE
                    eno <= '1';
                    numberout <= numberin;
                END IF;
            END IF;
        END IF;
    END PROCESS;

END behavior;