tsuckow

Untitled

Mar 10th, 2011
93
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. module ThermoProcessor
  2. (
  3.     clock,
  4.     sig_tick
  5. );
  6.  
  7. input clock;
  8. output sig_tick;
  9.  
  10. //
  11. //Processor
  12.  
  13. //Wishbone Common
  14. wire wb_clk = clock;
  15. wire wb_rst = 1'b0;
  16.  
  17. // Instruction master i/f wires
  18. wire [31:0] wb_rim_adr_o;
  19. wire          wb_rim_cyc_o;
  20. wire [31:0] wb_rim_dat_i;
  21. wire [31:0] wb_rim_dat_o;
  22. wire [3:0]  wb_rim_sel_o;
  23. wire        wb_rim_ack_i;
  24. wire        wb_rim_err_i;
  25. wire        wb_rim_rty_i = 1'b0;
  26. wire        wb_rim_we_o;
  27. wire        wb_rim_stb_o;
  28. wire        wb_rim_cti_o;
  29. wire        wb_rim_bte_o;
  30.  
  31. // Data master i/f wires
  32. wire [31:0] wb_rdm_adr_o;
  33. wire        wb_rdm_cyc_o;
  34. wire [31:0] wb_rdm_dat_i;
  35. wire [31:0] wb_rdm_dat_o;
  36. wire [3:0]  wb_rdm_sel_o;
  37. wire        wb_rdm_ack_i;
  38. wire        wb_rdm_err_i;
  39. wire        wb_rdm_rty_i = 1'b0;
  40. wire        wb_rdm_we_o;
  41. wire        wb_rdm_stb_o;
  42. wire        wb_rdm_cti_o;
  43. wire        wb_rdm_bte_o;
  44.  
  45. // Debug i/f wires
  46. wire [3:0]  dbg_lss;
  47. wire [1:0]  dbg_is;
  48. wire [10:0] dbg_wp;
  49. wire        dbg_bp;
  50. wire [31:0] dbg_dat_dbg;
  51. wire [31:0] dbg_dat_risc;
  52. wire [31:0] dbg_adr;
  53. wire        dbg_ewt;
  54. wire        dbg_stall;
  55. wire [2:0]  dbg_op;
  56.  
  57. or1200_top proc
  58. (
  59.  
  60.     .rst_i      ( wb_rst ),
  61.     .clk_i      ( wb_clk ),
  62.  
  63.     .clmode_i   ( 2'b00 ), // 1 to 1 clock?
  64.  
  65.     // WISHBONE Instruction Master
  66.     .iwb_clk_i  ( wb_clk ),
  67.     .iwb_rst_i  ( wb_rst ),
  68.     .iwb_cyc_o  ( wb_rim_cyc_o ),
  69.     .iwb_adr_o  ( wb_rim_adr_o ),
  70.     .iwb_dat_i  ( wb_rim_dat_i ),
  71.     .iwb_dat_o  ( wb_rim_dat_o ),
  72.     .iwb_sel_o  ( wb_rim_sel_o ),
  73.     .iwb_ack_i  ( wb_rim_ack_i ),
  74.     .iwb_err_i  ( wb_rim_err_i ),
  75.     .iwb_rty_i  ( wb_rim_rty_i ),
  76.     .iwb_we_o   ( wb_rim_we_o  ),
  77.     .iwb_stb_o  ( wb_rim_stb_o ),
  78.     .iwb_cti_o  ( wb_rim_cti_o ),
  79.     .iwb_bte_o  ( wb_rim_bte_o ),
  80.  
  81.     // WISHBONE Data Master
  82.     .dwb_clk_i  ( wb_clk ),
  83.     .dwb_rst_i  ( wb_rst ),
  84.     .dwb_cyc_o  ( wb_rdm_cyc_o ),
  85.     .dwb_adr_o  ( wb_rdm_adr_o ),
  86.     .dwb_dat_i  ( wb_rdm_dat_i ),
  87.     .dwb_dat_o  ( wb_rdm_dat_o ),
  88.     .dwb_sel_o  ( wb_rdm_sel_o ),
  89.     .dwb_ack_i  ( wb_rdm_ack_i ),
  90.     .dwb_err_i  ( wb_rdm_err_i ),
  91.     .dwb_rty_i  ( wb_rdm_rty_i ),
  92.     .dwb_we_o   ( wb_rdm_we_o  ),
  93.     .dwb_stb_o  ( wb_rdm_stb_o ),
  94.     .dwb_cti_o  ( wb_rdm_cti_o ),
  95.     .dwb_bte_o  ( wb_rdm_bte_o ),
  96.  
  97.     // Debug
  98.     .dbg_stall_i( dbg_stall ),
  99.     .dbg_dat_i  ( dbg_dat_dbg ),
  100.     .dbg_adr_i  ( dbg_adr ),
  101.     .dbg_ewt_i  ( 1'b0 ),
  102.     .dbg_lss_o  ( dbg_lss ),
  103.     .dbg_is_o   ( dbg_is ),
  104.     .dbg_wp_o   ( dbg_wp ),
  105.     .dbg_bp_o   ( dbg_bp ),
  106.     .dbg_dat_o  ( dbg_dat_risc ),
  107.    
  108.     //Not all are accounted for ?
  109.     //dbg_stall_i, dbg_ewt_i,   dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
  110.     //dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
  111.  
  112.     // Power Management
  113.     .pm_clksd_o ( ),
  114.     .pm_cpustall_i  ( 1'b0 ),
  115.     .pm_dc_gate_o   ( ),
  116.     .pm_ic_gate_o   ( ),
  117.     .pm_dmmu_gate_o ( ),
  118.     .pm_immu_gate_o ( ),
  119.     .pm_tt_gate_o   ( ),
  120.     .pm_cpu_gate_o  ( ),
  121.     .pm_wakeup_o    ( ),
  122.     .pm_lvolt_o ( ),
  123.  
  124.     // Interrupts
  125.     .pic_ints_i ( 20'b0 ),
  126.  
  127.     .sig_tick(sig_tick)
  128. );
  129.  
  130. //
  131. //Instruction Wishbone Bus
  132. ram_wb INST_RAM
  133. (
  134.     .dat_i(wb_rim_dat_o),
  135.     .dat_o(wb_rim_dat_i),
  136.     .adr_i(wb_rim_adr_o),
  137.     .we_i (wb_rim_we_o),
  138.     .sel_i(wb_rim_sel_o),
  139.     .cyc_i(wb_rim_cyc_o),
  140.     .stb_i(wb_rim_stb_o),
  141.     .ack_o(wb_rim_ack_i),
  142.     .cti_i(wb_rim_cti_o),
  143.     .clk_i(wb_clk),
  144.     .rst_i(wb_rst)
  145. );
  146.  
  147. endmodule
RAW Paste Data