static SOA_Error Set7179ToNTSC(SOA_PContext pContext)
{
	SOA_Error error_code = SOA_E_NONE;
	ADI_DEV_DEVICE_HANDLE *pDev = pContext->tag;
    // ADV7179 register configuration array for NTSC mode
    ADI_DEV_ACCESS_REGISTER ADV7179_Cfg[]={
    	/**
    	 * MODE REGISTER 0 (MR0) => 0b00000000
    	 * -----------------------------------
    	 *
    	 * |_.Name                           |_.Value                  |_.Bits |
    	 * | Chroma Filter Select            | 1.3 MHz LOW-PASS FILTER | 0b000 |
    	 * | Luma Filter Select              | LOW-PASS FILTER (NTSC)  | 0b000 |
    	 * | Output Video Standard Selection | NTSC                    | 0b00  |
    	 **/
    	{ADV717x_MR0, 	0x00},
    	/**
    	 * MODE REGISTER 1 (MR1) => 0b01011000
    	 * -----------------------------------
    	 *
    	 * |_.Name                          |_.Value      |_.Bits |
    	 * | Color Bar Control              | DISABLE     | 0b0   |
    	 * | DAC A Control                  | POWER-DOWN  | 0b1   |
    	 * | DAC B Control                  | NORMAL      | 0b0   |
    	 * | RESERVED (should be 1)         | NULL        | 0b1   |
    	 * | DAC C Control                  | POWER-DOWN  | 0b1   |
    	 * | Closed Captioning Field Select | NO DATA OUT | 0b00  |
    	 * | Interlace Control              | INTERLACED  | 0b0   |
    	 **/
    	{ADV717x_MR1, 	0x58},
    	/**
    	 * MODE REGISTER 2 (MR2) => 0b00000000
    	 * -----------------------------------
		 *
    	 * |_.Name                      |_.Value           |_.Bits |
    	 * | RESERVERD                  | NULL             | 0b0   |
    	 * | Low Power Mode             | DISABLE          | 0b0   |
    	 * | Burst Control              | ENABLE BURST     | 0b0   |
    	 * | Chrominince Control        | ENABLE COLOR     | 0b0   |
    	 * | Active Video Line Duration | 720 PIXELS       | 0b0   |
    	 * | Genlock Control            | DISABLE GENLOCK  | 0b00  |
    	 * | Square Pixle Control       | DISABLE          | 0b0   |
    	 **/
    	{ADV717x_MR2, 	0x00},
    	/**
    	 * MODE REGISTER 3 (MR3) => 0b00000000
     	 * -----------------------------------
     	 *
    	 * |_.Name                   |_.Value  |_.Bits |
    	 * | Input Default Color     | DISABLE | 0b0   |
    	 * | TTREXQ Bit Mode Control | NORMAL  | 0b0   |
    	 * | TELETEXT Enable         | DISABLE | 0b0   |
    	 * | Chroma Output Select    | DISABLE | 0b0   |
    	 * | DAC Output              | NORMAL  | 0b0   |
    	 * | VBI_Open				 | DISABLE | 0b0   |
    	 * | RESERVED                | NULL    | 0b00  |
    	 **/
    	{ADV717x_MR3, 	0x00},
    	/**
    	 *
    	 * MODE REGISTER 4 (MR4) => 0b00010000
    	 * -----------------------------------
    	 *
    	 * |_.Name                       |_.Value      |_.Bits |
    	 * | RESERVED (should be 0)      | NULL        | 0b0   |
    	 * | Sleep Mode Control          | DISABLE     | 0b0   |
    	 * | Active Video Filter Control | DISABLE     | 0b0   |
    	 * | Pedestal Control            | PEDESTAL ON | 0b1   |
    	 * | VSYNC_3H                    | DISABLE     | 0b0   |
    	 * | RGB SYNC                    | DISABLE     | 0b0   |
    	 * | RGB/YUV Control             | RGB OUTPUT  | 0b0   |
    	 * | Output Select               | YC Output   | 0b0   |
    	 **/
    	{ADV717x_MR4, 	0x10},
    	/**
    	 * TIMING MODE REGISTER 0 (TR0) => 0b00000000
    	 * ------------------------------------------
    	 *
    	 * |_.Name                 |_.Value       |_.Bits |
    	 * | Timing Register Reset |              | 0b0   |
    	 * | Pixel Port Control    | 8 BIT        | 0b0   |
    	 * | Luma Delay            | 0ns DELAY    | 0b00  |
    	 * | Blank Input Control   | ENABLE       | 0b0   |
    	 * | Timing Mode Selection | MODE 0       | 0b00  |
    	 * | Master/Slave Control  | SLAVE TIMING | 0b0   |
    	 **/
    	{ADV717x_TMR0, 	0x00},
		/**
    	 * TIMING MODE REGISTER 1 (TR1) => 0b00000000
    	 * ------------------------------------------
    	 *
    	 * |_.Name                            |_.Value  |_.Bits |
    	 * | HSYNC to Pixel Data Adjust       | 0xTpclk | 0b00  |
    	 * | HSYNC to Field Rising Edge Delay | Tb      | 0b00  |
    	 * | HSYNC to Field/Vsync Delay       | 0xTpclk | 0b00  |
    	 * | HSYNC Width                      | 1xTpclk | 0b00  |
    	 **/
    	{ADV717x_TMR1, 	0x00},
       	{ADI_DEV_REGEND,NULL}
    };	// End of register access

    E(adi_dev_Control(
    	*pDev,
    	ADI_ADV717x_CMD_SET_SCF_REG,
    	(void *) ADV717x_SCF_VALUE_NTSC)
    );

   // configure ADV7179 in selected mode
    E(adi_dev_Control(
      	*pDev,
      	ADI_DEV_CMD_REGISTER_TABLE_WRITE,
    	(void *)ADV7179_Cfg)
    );
    return SOA_E_NONE;
FuncError:
	return error_code;
}