LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.ITCE211Project_library.ALL;

ENTITY pe_array IS

    PORT (
         reset, clk : IN STD_LOGIC;
		   eni : in std_logic := '0';
        numberin : IN STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0):= (OTHERS => '0');
         numbercotnacted: OUT STD_LOGIC_VECTOR (data_output - 1 DOWNTO 0) := (OTHERS => '0');
			input : in std_logic_vector(number_of_pe*data_width - 1 downto 0)

    );
END ENTITY;

ARCHITECTURE rtl OF pe_array IS
    COMPONENT pe IS
        PORT (
            numberin : IN STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
            numberout : OUT STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
            clk, eni, reset : IN STD_LOGIC;
            eno : OUT STD_LOGIC
        );

    END COMPONENT;
    ----------------------Signals-------------------------------------
	 signal enablesig : std_logic_vector( number_of_pe - 1 DOWNTO 0) := (OTHERS => '0');
    SIGNAL number : vector_array(number_of_pe - 1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));


    signal sig1 : my_customtype ;

BEGIN
    ----------------------Generate component-------------------------------------
    Gen_PE : FOR i IN 0 TO number_of_PE - 1 GENERATE
        Gen_PE0 : IF i = 0 GENERATE
            Processing_Element : pe PORT MAP(
                numberin => numberin,
                numberout => number(1),
                eno => enablesig(1),
                clk => clk,
                reset => reset,
                eni => eni);

        END GENERATE Gen_PE0;
        Gen_PE1 : IF i > 0 AND i < number_of_PE - 1 GENERATE
            Processing_Element : pe PORT MAP(
                numberin => number(i),
                eni => enablesig(i),
                numberout => number(i + 1),
                eno => enablesig(i + 1),
                clk => clk,
                reset => reset);
        END GENERATE Gen_PE1;
        Gen_PE2 : IF i = number_of_PE - 1 GENERATE
            Processing_Element : pe PORT MAP(
                numberin => number(i),
                eni => enablesig(i),
                numberout => number(0),
                eno => OPEN,
                clk => clk,
                reset => reset
            );
        END GENERATE Gen_PE2;

    END GENERATE Gen_PE;

    concatenting : PROCESS (number) IS
    BEGIN
            L1 : FOR i IN 0 TO number_of_pe - 1 LOOP
                numbercotnacted((data_width - 1) + i * data_width  DOWNTO 0 + i *data_width ) <= number(i);
            END LOOP L1;
    END PROCESS concatenting;


	 slicing:for i in 0 to data_width - 1 generate
            sig1(i) <= input(data_width*(i+1)-1 downto data_width*i);
        end generate;




END ARCHITECTURE;