library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test is
end test;

architecture Behavioral of test is
    component FSM is
        Port (
            CLK : in STD_LOGIC;
            RST : in STD_LOGIC;
            FRONT_SENSOR : in STD_LOGIC;
            BACK_SENSOR : in STD_LOGIC;
            PASSWORD_1 : in STD_LOGIC_VECTOR(1 downto 0);
            PASSWORD_2 : in STD_LOGIC_VECTOR(1 downto 0);
            GREEN_LED : inout STD_LOGIC;
            RED_LED : inout STD_LOGIC
        );
    end component;
    SIGNAL CLK : STD_LOGIC;
    SIGNAL RST : STD_LOGIC;
    SIGNAL FRONT_SENSOR : STD_LOGIC;
    SIGNAL BACK_SENSOR : STD_LOGIC;
    SIGNAL PASSWORD_1 : STD_LOGIC_VECTOR(1 downto 0);
    SIGNAL PASSWORD_2 : STD_LOGIC_VECTOR(1 downto 0);
    SIGNAL GREEN_LED : STD_LOGIC;
    SIGNAL RED_LED : STD_LOGIC;
begin
    car_parking : fsm port map(
        clk=>clk,rst=>rst,front_sensor=>front_sensor,back_sensor=>back_sensor,
        password_1=>password_1,password_2=>password_2,green_led=>green_led,red_led=>red_led
    );

    process begin
        wait for 15ns;
        clk<='0';
        wait for 15ns;
        clk<='1';
    end process;

    process begin
        wait for 100ns;
        rst<='1';
        wait until falling_edge(clk);
        rst<='0';
        front_sensor<='1';
        password_1<="11";
        password_2<="11";
        wait until green_led='1';
        back_sensor<='1';
        password_1<="10";
        wait until falling_edge(clk);
        back_sensor<='0';
        wait until falling_edge(clk);
        password_1<="11";
        wait until falling_edge(clk);
        front_sensor<='0';
        back_sensor<='1';
        wait until falling_edge(clk);
        back_sensor<='0';
    end process;
end Behavioral;