// SISTEMAS DIGITAIS - UFRN (17/08/18)
// SOMADOR DE 2 BITS

library ieee;
use ieee.std_logic_1164.all;

entity soma2 is
port(
    X0, X1: in std_logic;
    Y0, Y1: in std_logic;
    C0, X2, Y2: out std_logic);
end soma2;

architecture archSoma2 of soma2 is
signal Ci   :   std_logic;
begin
    Ci <= Y0 and Y1;
    Y2 <= Y0 xor Y1;
    X2 <= (not (X0) and (X1 xor Ci)) or ((X0) and (X1 xnor Ci));
    C0 <= (X1 and Ci) or (X0 and (X1 xor Ci));

end archSoma2;