`include "constants.vams"
`include "disciplines.vams"

module encoder(input0, input1, input2, input3, input4, input5, input6, input7, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, K, clk);

input input0, input1, input2, input3, input4, input5, input6, input7, clk, K;
output d0, d1, d2, d3, d4, d5, d6, d7, d8, d9;
electrical d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, input0, input1, input2, input3, input4, input5, input6, input7, clk, K;
parameter real vtrans_clk = 0.4;

integer dispout, dispin;
integer ai, bi, ci, di, ei, fi, gi, hi, ki, illegalk;
integer aeqb, ceqd, l22, l40, l04, l13, l31, ao, bo, co, do, eo, io, pd1s6, nd1s6, ndos6, pdos6, alt7, fo, go, ho, jo, ndos4, pdos4, nd1s4, pd1s4, llegalk, compls6, disp6, compls4;
real t_d0, t_d1, t_d2, t_d3, t_d4, t_d5, t_d6, t_d7, t_d8, t_d9;

parameter real vtrans = 0.4;
parameter real vdd = 0.8;


analog begin
@ ( initial_step ) begin
    dispout = 1;
      end
//Load data
@ (cross( V(clk) - vtrans_clk, +1)) begin
ai = V(input0) > vtrans;
bi = V(input1) > vtrans;
ci = V(input2) > vtrans;
di = V(input3) > vtrans;
ei = V(input4) > vtrans;
fi = V(input5) > vtrans;
gi = V(input6) > vtrans;
hi = V(input7) > vtrans;
ki = V(K) > vtrans;
dispin = 0;

 aeqb = (ai & bi) | (!ai & !bi) ;
 ceqd = (ci & di) | (!ci & !di) ;
 l22 = (ai & bi & !ci & !di) |
         (ci & di & !ai & !bi) |
         ( !aeqb & !ceqd) ;
 l40 = ai & bi & ci & di ;
 l04 = !ai & !bi & !ci & !di ;
 l13 = ( !aeqb & !ci & !di) |
         ( !ceqd & !ai & !bi) ;
 l31 = ( !aeqb & ci & di) |
         ( !ceqd & ai & bi) ;

  // The 5B/6B encoding

 ao = ai ;
 bo = (bi & !l40) | l04 ;
 co = l04 | ci | (ei & di & !ci & !bi & !ai) ;
 do = di & ! (ai & bi & ci) ;
 eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai) ;
 io = (l22 & !ei) |
        (ei & !di & !ci & !(ai&bi)) |  // D16, D17, D18
        (ei & l40) |
        (ki & ei & di & ci & !bi & !ai) | // K.28
        (ei & !di & ci & !bi & !ai) ;

  // pds16 indicates cases where d-1 is assumed + to get our encoded value
 pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31) ;
  // nds16 indicates cases where d-1 is assumed - to get our encoded value
 nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai) ;

  // ndos6 is pds16 cases where d-1 is + yields - disp out - all of them
 ndos6 = pd1s6 ;
  // pdos6 is nds16 cases where d-1 is - yields + disp out - all but one
 pdos6 = ki | (ei & !l22 & !l13) ;


  // some Dx.7 and all Kx.7 cases result in run length of 5 case unless
  // an alternate coding is used (referred to as Dx.A7, normal is Dx.P7)
  // specifically, D11, D13, D14, D17, D18, D19.
 alt7 = fi & gi & hi & (ki |
                  			(dispin ? (!ei & di & l31) : (ei & !di & l13))) ;


 fo = fi & ! alt7 ;
 go = gi | (!fi & !gi & !hi) ;
 ho = hi ;
 jo = (!hi & (gi ^ fi)) | alt7 ;

  // nd1s4 is cases where d-1 is assumed - to get our encoded value
 nd1s4 = fi & gi ;
  // pd1s4 is cases where d-1 is assumed + to get our encoded value
 pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ;

  // ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some
 ndos4 = (!fi & !gi) ;
  // pdos4 is nd1s4 cases where d-1 is - yields + disp out
 pdos4 = fi & gi & hi ;

  // only legal K codes are K28.0->.7, K23/27/29/30.7
  //    K28.0->7 is ei=di=ci=1,bi=ai=0
  //    K23 is 10111
  //    K27 is 11011
  //    K29 is 11101
  //    K30 is 11110 - so K23/27/29/30 are ei & l31
 illegalk = ki &
          (ai | bi | !ci | !di | !ei) & // not K28.0->7
          (!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7

  // now determine whether to do the complementing
  // complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set
 compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin) ;

  // disparity out of 5b6b is disp in with pdso6 and ndso6
  // pds16 indicates cases where d-1 is assumed + to get our encoded value
  // ndos6 is cases where d-1 is + yields - disp out
  // nds16 indicates cases where d-1 is assumed - to get our encoded value
  // pdos6 is cases where d-1 is - yields + disp out
  // disp toggles in all ndis16 cases, and all but that 1 nds16 case

 disp6 = dispin ^ (ndos6 | pdos6) ;

 compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6) ;
 dispout = disp6 ^ (ndos4 | pdos4) ;

t_d0 = (jo ^ compls4);
t_d1 = (ho ^ compls4);
t_d2 = (go ^ compls4);
t_d3 = (fo ^ compls4);
t_d4 = (io ^ compls6);
t_d5 = (eo ^ compls6);
t_d6 = (do ^ compls6);
t_d7 = (co ^ compls6);
t_d8 = (bo ^ compls6);
t_d9 = (ao ^ compls6);

end
V(d0) <+ t_d0*vdd;
V(d1) <+ t_d1*vdd;
V(d2) <+ t_d2*vdd;
V(d3) <+ t_d3*vdd;
V(d4) <+ t_d4*vdd;
V(d5) <+ t_d5*vdd;
V(d6) <+ t_d6*vdd;
V(d7) <+ t_d7*vdd;
V(d8) <+ t_d8*vdd;
V(d9) <+ t_d9*vdd;

end
endmodule