module clock_divider_1Hz(
  input wire  clock_50MHz, // PIN_M9
  output wire clock_1Hz
);
  reg [25:0] count;

  assign clock_1Hz = count[25];

  always @ (posedge clock_50MHz) begin
	if (count > 26'd50000000) begin
	  count <= 26'd0;
	end else begin
	  count <= count + 1'b1;
	end

  end


endmodule