module numarator1
    (input clk, rst,
    output [3:0] q,sec;
    reg [31:0] q_nxt, q_reg,flag_reg;

    assign q = q_reg;
	 assign flag=flag_reg;
//always block for sequential part
always @( posedge clk or posedge rst)
begin
    if (rst)
        q_reg <= 0;
    else
        q_reg <= q_nxt;

end

always @(*)
begin
  sec= 0;
  q_nxt = q_reg + 1;
			if(q_reg == 50)
			begin
				sec = 1;
				q_nxt = 0;
			end

		if(rst)
			flag_reg<=0;
		else
		  if(sec==1)
				flag_reg <= ~flag_reg;
			end
		end

end


endmodule