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Dell M4400 Flashrom Clean

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Mar 25th, 2017
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  1. ~/flashrom $ sudo ./flashrom --programmer internal:laptop=force_I_want_a_brick -V
  2. flashrom v0.9.9-r1954 on Linux 3.11.0-26-generic (x86_64)
  3. flashrom is free software, get the source code at https://flashrom.org
  4.  
  5. flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian
  6. Command line (3 args): ./flashrom --programmer internal:laptop=force_I_want_a_brick -V
  7. Calibrating delay loop... OS timer resolution is 2 usecs, 2912M loops per second, 10 myus = 11 us, 100 myus = 112 us, 1000 myus = 1025 us, 10000 myus = 10027 us, 8 myus = 16 us, OK.
  8. Initializing internal programmer
  9. No coreboot table found.
  10. Using Internal DMI decoder.
  11. DMI string chassis-type: "Portable"
  12. Laptop detected via DMI.
  13. DMI string system-manufacturer: "Dell Inc."
  14. DMI string system-product-name: "Precision M4400 "
  15. DMI string system-version: "Not Specified"
  16. DMI string baseboard-manufacturer: "Dell Inc."
  17. DMI string baseboard-product-name: "0R906R"
  18. DMI string baseboard-version: " "
  19. ========================================================================
  20. WARNING! You seem to be running flashrom on an unsupported laptop.
  21. Laptops, notebooks and netbooks are difficult to support and we
  22. recommend to use the vendor flashing utility. The embedded controller
  23. (EC) in these machines often interacts badly with flashing.
  24. See the manpage and https://flashrom.org/Laptops for details.
  25.  
  26. If flash is shared with the EC, erase is guaranteed to brick your laptop
  27. and write may brick your laptop.
  28. Read and probe may irritate your EC and cause fan failure, backlight
  29. failure and sudden poweroff.
  30. You have been warned.
  31. ========================================================================
  32. Proceeding anyway because user forced us to.
  33. Found chipset "Intel ICH9M-E" with PCI ID 8086:2917.
  34. Enabling flash write... Root Complex Register Block address = 0xfed18000
  35. GCS = 0x140440: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1 (SPI)
  36. Top Swap: not enabled
  37. 0xfff80000/0xffb80000 FWH IDSEL: 0x0
  38. 0xfff00000/0xffb00000 FWH IDSEL: 0x0
  39. 0xffe80000/0xffa80000 FWH IDSEL: 0x0
  40. 0xffe00000/0xffa00000 FWH IDSEL: 0x0
  41. 0xffd80000/0xff980000 FWH IDSEL: 0x0
  42. 0xffd00000/0xff900000 FWH IDSEL: 0x0
  43. 0xffc80000/0xff880000 FWH IDSEL: 0x0
  44. 0xffc00000/0xff800000 FWH IDSEL: 0x0
  45. 0xff700000/0xff300000 FWH IDSEL: 0x0
  46. 0xff600000/0xff200000 FWH IDSEL: 0x0
  47. 0xff500000/0xff100000 FWH IDSEL: 0x0
  48. 0xff400000/0xff000000 FWH IDSEL: 0x0
  49. 0xfff80000/0xffb80000 FWH decode enabled
  50. 0xfff00000/0xffb00000 FWH decode enabled
  51. 0xffe80000/0xffa80000 FWH decode enabled
  52. 0xffe00000/0xffa00000 FWH decode enabled
  53. 0xffd80000/0xff980000 FWH decode disabled
  54. 0xffd00000/0xff900000 FWH decode disabled
  55. 0xffc80000/0xff880000 FWH decode disabled
  56. 0xffc00000/0xff800000 FWH decode disabled
  57. 0xff700000/0xff300000 FWH decode disabled
  58. 0xff600000/0xff200000 FWH decode disabled
  59. 0xff500000/0xff100000 FWH decode disabled
  60. 0xff400000/0xff000000 FWH decode disabled
  61. Maximum FWH chip size: 0x200000 bytes
  62. SPI Read Configuration: prefetching enabled, caching enabled,
  63. BIOS_CNTL = 0x0a: BIOS Lock Enable: enabled, BIOS Write Enable: disabled
  64. Warning: Setting Bios Control at 0xdc from 0x0a to 0x09 failed.
  65. New value is 0x0a.
  66. SPIBAR = 0x00007fda3db7b000 + 0x3800
  67. 0x04: 0x6008 (HSFS)
  68. HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0
  69. Programming OPCODES... done
  70. 0x06: 0x0000 (HSFC)
  71. HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0
  72. 0x50: 0x00001a1b (FRAP)
  73. BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b
  74. 0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
  75. 0x58: 0x03ff0260 FREG1: BIOS region (0x00260000-0x003fffff) is read-write.
  76. 0x5C: 0x025f000b FREG2: Warning: Management Engine region (0x0000b000-0x0025ffff) is locked.
  77. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write.
  78. 0x64: 0x000a0003 FREG4: Platform Data region (0x00003000-0x0000afff) is read-write.
  79. Not all flash regions are freely accessible by flashrom. This is most likely
  80. due to an active ME. Please see https://flashrom.org/ME for details.
  81. Writes have been disabled for safety reasons. You can enforce write
  82. support with the ich_spi_force programmer option, but you will most likely
  83. harm your hardware! If you force flashrom you will get no support if
  84. something breaks. On a few mainboards it is possible to enable write
  85. access by setting a jumper (see its documentation or the board itself).
  86. 0x90: 0x04 (SSFS)
  87. SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0
  88. 0x91: 0x004060 (SSFC)
  89. SSFC: SCGO=0, ACS=0, SPOP=0, COP=6, DBC=0, SME=0, SCF=0
  90. 0x94: 0x5006 (PREOP)
  91. 0x96: 0x463b (OPTYPE)
  92. 0x98: 0x05d80302 (OPMENU)
  93. 0x9C: 0xc79f0190 (OPMENU+4)
  94. 0xA0: 0x00000000 (BBAR)
  95. 0xC4: 0x00002005 (LVSCC)
  96. LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0
  97. 0xC8: 0x00002005 (UVSCC)
  98. UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
  99. 0xD0: 0x00000000 (FPB)
  100. PROBLEMS, continuing anyway
  101. The following protocols are supported: FWH, SPI.
  102. Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016
  103. Found Macronix flash chip "MX25L3205(A)" (4096 kB, SPI) mapped at physical address 0x00000000ffc00000.
  104. Chip status register is 0x00.
  105. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set
  106. Chip status register: Bit 6 is not set
  107. Chip status register: Bit 5 is not set
  108. Chip status register: Block Protect 2 (BP2) is not set
  109. Chip status register: Block Protect 1 (BP1) is not set
  110. Chip status register: Block Protect 0 (BP0) is not set
  111. Chip status register: Write Enable Latch (WEL) is not set
  112. Chip status register: Write In Progress (WIP/BUSY) is not set
  113. Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016
  114. Found Macronix flash chip "MX25L3205D/MX25L3208D" (4096 kB, SPI) mapped at physical address 0x00000000ffc00000.
  115. Chip status register is 0x00.
  116. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set
  117. Chip status register: Bit 6 is not set
  118. Chip status register: Block Protect 3 (BP3) is not set
  119. Chip status register: Block Protect 2 (BP2) is not set
  120. Chip status register: Block Protect 1 (BP1) is not set
  121. Chip status register: Block Protect 0 (BP0) is not set
  122. Chip status register: Write Enable Latch (WEL) is not set
  123. Chip status register: Write In Progress (WIP/BUSY) is not set
  124. Probing for Macronix MX25L3206E/MX25L3208E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016
  125. Found Macronix flash chip "MX25L3206E/MX25L3208E" (4096 kB, SPI) mapped at physical address 0x00000000ffc00000.
  126. Chip status register is 0x00.
  127. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set
  128. Chip status register: Bit 6 is not set
  129. Chip status register: Block Protect 3 (BP3) is not set
  130. Chip status register: Block Protect 2 (BP2) is not set
  131. Chip status register: Block Protect 1 (BP1) is not set
  132. Chip status register: Block Protect 0 (BP0) is not set
  133. Chip status register: Write Enable Latch (WEL) is not set
  134. Chip status register: Write In Progress (WIP/BUSY) is not set
  135. Probing for Macronix MX25L3273E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016
  136. Found Macronix flash chip "MX25L3273E" (4096 kB, SPI) mapped at physical address 0x00000000ffc00000.
  137. Chip status register is 0x00.
  138. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set
  139. Chip status register: Bit 6 is not set
  140. Chip status register: Block Protect 3 (BP3) is not set
  141. Chip status register: Block Protect 2 (BP2) is not set
  142. Chip status register: Block Protect 1 (BP1) is not set
  143. Chip status register: Block Protect 0 (BP0) is not set
  144. Chip status register: Write Enable Latch (WEL) is not set
  145. Chip status register: Write In Progress (WIP/BUSY) is not set
  146. Multiple flash chip definitions match the detected chip(s): "MX25L3205(A)", "MX25L3205D/MX25L3208D", "MX25L3206E/MX25L3208E", "MX25L3273E"
  147. Please specify which chip definition to use with the -c <chipname> option.
  148. Restoring MMIO space at 0x7fda3db7e8a0
  149. Restoring MMIO space at 0x7fda3db7e89c
  150. Restoring MMIO space at 0x7fda3db7e898
  151. Restoring MMIO space at 0x7fda3db7e896
  152. Restoring MMIO space at 0x7fda3db7e894
  153. Restoring PCI config space for 00:1f:0 reg 0xdc
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