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  1. `timescale 1ns / 1ps
  2. module projectCPU(clk, rst, data_fromRAM, wrEn, addr_toRAM, data_toRAM, pCounter);
  3.  
  4. parameter SIZE = 10;
  5.  
  6. input clk, rst;
  7. input wire [15:0] data_fromRAM;
  8. output reg wrEn;
  9. output reg [SIZE-1:0] addr_toRAM;
  10. output reg [15:0] data_toRAM;
  11. output reg [SIZE-1:0] pCounter;
  12.  
  13. // internal signals
  14. reg [2:0] opcode, opcodeNext;
  15. reg [12:0] operand, operandNext;
  16. reg [SIZE-1:0] pCounterNext;
  17. reg [15:0] W, WNext;
  18. reg [3:0] state, stateNext;
  19.  
  20.  
  21. always @(posedge clk) begin
  22. state <= #1 stateNext;
  23. pCounter <= #1 pCounterNext;
  24. opcode <= #1 opcodeNext;
  25. operand <= #1 operandNext;
  26. W <= #1 WNext;
  27. end
  28.  
  29. always @(*) begin
  30. stateNext = state;
  31. pCounterNext = pCounter;
  32. opcodeNext = opcode;
  33. operandNext = operand;
  34. WNext = W;
  35. addr_toRAM = 0;
  36. wrEn = 0;
  37. data_toRAM = 0;
  38.  
  39. if(rst) begin
  40. stateNext = 0;
  41. pCounterNext = 0;
  42. opcodeNext = 0;
  43. operandNext = 0;
  44. WNext = 0;
  45. addr_toRAM = 0;
  46. wrEn = 0;
  47. data_toRAM = 0;
  48. end
  49.  
  50. else
  51. case(state)
  52.  
  53. 0: begin // TAKE INSTRUCTION
  54. pCounterNext = pCounter;
  55. opcodeNext = opcode;
  56. operandNext = operand;
  57. WNext = W;
  58. addr_toRAM = pCounter;
  59. wrEn = 0;
  60. data_toRAM = 0;
  61. stateNext = 1;
  62. end
  63.  
  64. 1: begin // TAKE *A
  65. pCounterNext = pCounter;
  66. opcodeNext = data_fromRAM[15:13];
  67. operandNext = data_fromRAM[12:0];
  68. WNext = W;
  69. addr_toRAM = data_fromRAM[12:0];
  70. wrEn = 0;
  71. data_toRAM = 0;
  72.  
  73. if (data_fromRAM[12:0] == 0) // Indirect
  74. begin
  75. addr_toRAM = 4;
  76. stateNext = 2;
  77. end
  78.  
  79. if (opcodeNext == 3'b000) // ADD
  80. stateNext = 3;
  81.  
  82. if (opcodeNext == 3'b001) // NAND
  83. stateNext = 4;
  84.  
  85. if (opcodeNext == 3'b010) // SRL
  86. stateNext = 5;
  87.  
  88. if (opcodeNext == 3'b011) // LT
  89. stateNext = 6;
  90.  
  91. if (opcodeNext == 3'b100) // BZ
  92. stateNext = 7;
  93.  
  94. if (opcodeNext == 3'b101) // CP2W
  95. stateNext = 8;
  96.  
  97. if (opcodeNext == 3'b110) // CPfW
  98. stateNext = 9;
  99.  
  100. if (opcodeNext == 3'b111) // MUL
  101. stateNext = 10;
  102. end
  103.  
  104. 2: begin // Indirect
  105. pCounterNext = pCounter;
  106. WNext = W;
  107. opcodeNext = opcode;
  108. operandNext = data_fromRAM;
  109. addr_toRAM = data_fromRAM;
  110. wrEn = 0;
  111. data_toRAM = 0;
  112.  
  113. if (opcodeNext == 3'b000) // ADD
  114. stateNext = 3;
  115.  
  116. if (opcodeNext == 3'b001) // NAND
  117. stateNext = 4;
  118.  
  119. if (opcodeNext == 3'b010) // SRL
  120. stateNext = 5;
  121.  
  122. if (opcodeNext == 3'b011) // LT
  123. stateNext = 6;
  124.  
  125. if (opcodeNext == 3'b100) // BZ
  126. stateNext = 7;
  127.  
  128. if (opcodeNext == 3'b101) // CP2W
  129. stateNext = 8;
  130.  
  131. if (opcodeNext == 3'b110) // CPfW
  132. stateNext = 9;
  133.  
  134. if (opcodeNext == 3'b111) // MUL
  135. stateNext = 10;
  136.  
  137. end
  138.  
  139. 3: begin // ADD
  140. pCounterNext = pCounter + 1;
  141. opcodeNext = opcode;
  142. operandNext = operand;
  143. addr_toRAM = operand;
  144. wrEn = 0;
  145. WNext = data_fromRAM + W; // *A + W
  146. stateNext = 0;
  147. end
  148.  
  149. 4: begin // NAND
  150. pCounterNext = pCounter + 1;
  151. opcodeNext = opcode;
  152. operandNext = operand;
  153. addr_toRAM = operand;
  154. wrEn = 0;
  155. WNext = ~(data_fromRAM & W); // (W = (*A) & W)
  156. stateNext = 0;
  157. end
  158.  
  159. 5: begin // SRL
  160. pCounterNext = pCounter + 1;
  161. opcodeNext = opcode;
  162. operandNext = operand;
  163. addr_toRAM = operand;
  164. wrEn = 0;
  165. if (data_fromRAM <= 16)
  166. begin
  167. WNext = W >> data_fromRAM;
  168. stateNext = 0;
  169. end
  170. if (data_fromRAM > 16)
  171. begin
  172. WNext = W << data_fromRAM - 16;
  173. stateNext = 0;
  174. end
  175. end
  176.  
  177. 6: begin // LT
  178. pCounterNext = pCounter + 1;
  179. opcodeNext = opcode;
  180. operandNext = operand;
  181. addr_toRAM = operand;
  182. wrEn = 0;
  183. WNext = W < data_fromRAM;
  184. stateNext = 0;
  185. end
  186.  
  187. 7: begin // BZ
  188. opcodeNext = opcode;
  189. operandNext = operand;
  190. addr_toRAM = operand;
  191. wrEn = 0;
  192. stateNext = 0;
  193. data_toRAM = 0;
  194. if (W == 0)
  195. pCounterNext = data_fromRAM;
  196. else
  197. pCounterNext = pCounter + 1;
  198. end
  199.  
  200. 8: begin // CP2W
  201. pCounterNext = pCounter + 1;
  202. opcodeNext = opcode;
  203. operandNext = operand;
  204. addr_toRAM = operand;
  205. wrEn = 0;
  206. WNext = data_fromRAM;
  207. stateNext = 0;
  208. end
  209.  
  210. 9: begin // CPfW
  211. pCounterNext = pCounter + 1;
  212. opcodeNext = opcode;
  213. operandNext = operand;
  214. addr_toRAM = operand;
  215. wrEn = 1;
  216. WNext = W;
  217. data_toRAM = W;
  218. stateNext = 0;
  219. end
  220.  
  221. 10: begin // MUL
  222. pCounterNext = pCounter + 1;
  223. opcodeNext = opcode;
  224. operandNext = operand;
  225. addr_toRAM = operand;
  226. wrEn = 0;
  227. WNext = data_fromRAM * W; // *A + W
  228. stateNext = 0;
  229. end
  230.  
  231. default: begin
  232. stateNext = 0;
  233. pCounterNext = 0;
  234. opcodeNext = 0;
  235. operandNext = 0;
  236. WNext = 0;
  237. addr_toRAM = 0;
  238. wrEn = 0;
  239. data_toRAM = 0;
  240. end
  241.  
  242. endcase
  243.  
  244. end
  245.  
  246. endmodule
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