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- `timescale 1ns / 1ps
- module projectCPU(clk, rst, data_fromRAM, wrEn, addr_toRAM, data_toRAM, pCounter);
- parameter SIZE = 10;
- input clk, rst;
- input wire [15:0] data_fromRAM;
- output reg wrEn;
- output reg [SIZE-1:0] addr_toRAM;
- output reg [15:0] data_toRAM;
- output reg [SIZE-1:0] pCounter;
- // internal signals
- reg [2:0] opcode, opcodeNext;
- reg [12:0] operand, operandNext;
- reg [SIZE-1:0] pCounterNext;
- reg [15:0] W, WNext;
- reg [3:0] state, stateNext;
- always @(posedge clk) begin
- state <= #1 stateNext;
- pCounter <= #1 pCounterNext;
- opcode <= #1 opcodeNext;
- operand <= #1 operandNext;
- W <= #1 WNext;
- end
- always @(*) begin
- stateNext = state;
- pCounterNext = pCounter;
- opcodeNext = opcode;
- operandNext = operand;
- WNext = W;
- addr_toRAM = 0;
- wrEn = 0;
- data_toRAM = 0;
- if(rst) begin
- stateNext = 0;
- pCounterNext = 0;
- opcodeNext = 0;
- operandNext = 0;
- WNext = 0;
- addr_toRAM = 0;
- wrEn = 0;
- data_toRAM = 0;
- end
- else
- case(state)
- 0: begin // TAKE INSTRUCTION
- pCounterNext = pCounter;
- opcodeNext = opcode;
- operandNext = operand;
- WNext = W;
- addr_toRAM = pCounter;
- wrEn = 0;
- data_toRAM = 0;
- stateNext = 1;
- end
- 1: begin // TAKE *A
- pCounterNext = pCounter;
- opcodeNext = data_fromRAM[15:13];
- operandNext = data_fromRAM[12:0];
- WNext = W;
- addr_toRAM = data_fromRAM[12:0];
- wrEn = 0;
- data_toRAM = 0;
- if (data_fromRAM[12:0] == 0) // Indirect
- begin
- addr_toRAM = 4;
- stateNext = 2;
- end
- if (opcodeNext == 3'b000) // ADD
- stateNext = 3;
- if (opcodeNext == 3'b001) // NAND
- stateNext = 4;
- if (opcodeNext == 3'b010) // SRL
- stateNext = 5;
- if (opcodeNext == 3'b011) // LT
- stateNext = 6;
- if (opcodeNext == 3'b100) // BZ
- stateNext = 7;
- if (opcodeNext == 3'b101) // CP2W
- stateNext = 8;
- if (opcodeNext == 3'b110) // CPfW
- stateNext = 9;
- if (opcodeNext == 3'b111) // MUL
- stateNext = 10;
- end
- 2: begin // Indirect
- pCounterNext = pCounter;
- WNext = W;
- opcodeNext = opcode;
- operandNext = data_fromRAM;
- addr_toRAM = data_fromRAM;
- wrEn = 0;
- data_toRAM = 0;
- if (opcodeNext == 3'b000) // ADD
- stateNext = 3;
- if (opcodeNext == 3'b001) // NAND
- stateNext = 4;
- if (opcodeNext == 3'b010) // SRL
- stateNext = 5;
- if (opcodeNext == 3'b011) // LT
- stateNext = 6;
- if (opcodeNext == 3'b100) // BZ
- stateNext = 7;
- if (opcodeNext == 3'b101) // CP2W
- stateNext = 8;
- if (opcodeNext == 3'b110) // CPfW
- stateNext = 9;
- if (opcodeNext == 3'b111) // MUL
- stateNext = 10;
- end
- 3: begin // ADD
- pCounterNext = pCounter + 1;
- opcodeNext = opcode;
- operandNext = operand;
- addr_toRAM = operand;
- wrEn = 0;
- WNext = data_fromRAM + W; // *A + W
- stateNext = 0;
- end
- 4: begin // NAND
- pCounterNext = pCounter + 1;
- opcodeNext = opcode;
- operandNext = operand;
- addr_toRAM = operand;
- wrEn = 0;
- WNext = ~(data_fromRAM & W); // (W = (*A) & W)
- stateNext = 0;
- end
- 5: begin // SRL
- pCounterNext = pCounter + 1;
- opcodeNext = opcode;
- operandNext = operand;
- addr_toRAM = operand;
- wrEn = 0;
- if (data_fromRAM <= 16)
- begin
- WNext = W >> data_fromRAM;
- stateNext = 0;
- end
- if (data_fromRAM > 16)
- begin
- WNext = W << data_fromRAM - 16;
- stateNext = 0;
- end
- end
- 6: begin // LT
- pCounterNext = pCounter + 1;
- opcodeNext = opcode;
- operandNext = operand;
- addr_toRAM = operand;
- wrEn = 0;
- WNext = W < data_fromRAM;
- stateNext = 0;
- end
- 7: begin // BZ
- opcodeNext = opcode;
- operandNext = operand;
- addr_toRAM = operand;
- wrEn = 0;
- stateNext = 0;
- data_toRAM = 0;
- if (W == 0)
- pCounterNext = data_fromRAM;
- else
- pCounterNext = pCounter + 1;
- end
- 8: begin // CP2W
- pCounterNext = pCounter + 1;
- opcodeNext = opcode;
- operandNext = operand;
- addr_toRAM = operand;
- wrEn = 0;
- WNext = data_fromRAM;
- stateNext = 0;
- end
- 9: begin // CPfW
- pCounterNext = pCounter + 1;
- opcodeNext = opcode;
- operandNext = operand;
- addr_toRAM = operand;
- wrEn = 1;
- WNext = W;
- data_toRAM = W;
- stateNext = 0;
- end
- 10: begin // MUL
- pCounterNext = pCounter + 1;
- opcodeNext = opcode;
- operandNext = operand;
- addr_toRAM = operand;
- wrEn = 0;
- WNext = data_fromRAM * W; // *A + W
- stateNext = 0;
- end
- default: begin
- stateNext = 0;
- pCounterNext = 0;
- opcodeNext = 0;
- operandNext = 0;
- WNext = 0;
- addr_toRAM = 0;
- wrEn = 0;
- data_toRAM = 0;
- end
- endcase
- end
- endmodule
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