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SallatielFernandes

porta_AND_dataflow

Nov 22nd, 2019
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VHDL 0.53 KB | None | 0 0
  1. --PROJETO: porta_AND_dataflow
  2. --ENTRADAS: A, B(in bit)
  3. --SAIDAS: S(out bit)
  4. --AUTORES: MARCOS MEIRA, JOAO VITOR, SALLATIEL FERNANDES
  5. --CRIACAO: 30/01/2018
  6. --ATUALIZACAO: 22/11/2019
  7. ----------------------------------------------------------
  8. entity porta_AND_dataflow is
  9.     port (A, B: in bit;
  10.              S: out bit);
  11. end porta_AND_dataflow;
  12. ----------------------------------------------------------
  13. architecture dataflow of porta_AND_dataflow is
  14. begin
  15.     S <= A and B;
  16. end dataflow;
  17. ----------------------------------------------------------
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