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  1. ****** START compiling CoreLab.Program:Caller() (MethodHash=4dbcbd65)
  2. Generating code for Windows x64
  3. OPTIONS: compCodeOpt = BLENDED_CODE
  4. OPTIONS: compDbgCode = true
  5. OPTIONS: compDbgInfo = true
  6. OPTIONS: compDbgEnC = false
  7. OPTIONS: compProcedureSplitting = false
  8. OPTIONS: compProcedureSplittingEH = false
  9. IL to import:
  10. IL_0000 00 nop
  11. IL_0001 28 03 00 00 06 call 0x6000003
  12. IL_0006 26 pop
  13. IL_0007 2a ret
  14.  
  15. lvaGrabTemp returning 0 (V00 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
  16. ; Initial local variable assignments
  17. ;
  18. ; V00 OutArgs lclBlk (na) "OutgoingArgSpace"
  19. *************** In compInitDebuggingInfo() for CoreLab.Program:Caller()
  20. getVars() returned cVars = 0, extendOthers = true
  21. info.compStmtOffsetsCount = 0
  22. info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE )
  23. *************** In fgFindBasicBlocks() for CoreLab.Program:Caller()
  24. Jump targets:
  25. none
  26. New Basic Block BB01 [0000] created.
  27. BB01 [000..008)
  28. CLFLG_MINOPT set for method CoreLab.Program:Caller()
  29. IL Code Size,Instr 8, 4, Basic Block count 1, Local Variable Num,Ref count 1, 0 for method CoreLab.Program:Caller()
  30. IL Code Size,Instr 8, 4, Basic Block count 1, Local Variable Num,Ref count 1, 0 for method CoreLab.Program:Caller()
  31. OPTIONS: opts.MinOpts() == true
  32. Basic block list for 'CoreLab.Program:Caller()'
  33.  
  34. -----------------------------------------------------------------------------------------------------------------------------------------
  35. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  36. -----------------------------------------------------------------------------------------------------------------------------------------
  37. BB01 [0000] 1 1 [000..008) (return)
  38. -----------------------------------------------------------------------------------------------------------------------------------------
  39. *************** In impImport() for CoreLab.Program:Caller()
  40.  
  41. impImportBlockPending for BB01
  42.  
  43. Importing BB01 (PC=000) of 'CoreLab.Program:Caller()'
  44. [ 0] 0 (0x000) nop
  45.  
  46. STMT00000 (IL 0x000... ???)
  47. [000000] ------------ * NO_OP void
  48.  
  49. [ 0] 1 (0x001) call 06000003
  50. In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
  51. HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Double
  52. Found type Hardware Intrinsic SIMD Vector128<double>
  53. Known type Vector128<double>
  54.  
  55. lvaGrabTemp returning 1 (V01 tmp1) called for impSpillStackEnsure.
  56. Known type Vector128<double>
  57.  
  58.  
  59. STMT00001 (IL 0x001... ???)
  60. [000004] -AC-G------- * ASG simd16 (copy)
  61. [000002] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  62. [000001] --C-G------- \--* CALL simd16 CoreLab.Program.Callee
  63.  
  64. [ 1] 6 (0x006) pop
  65. ... CEE_POP struct ...
  66. [000005] ------------ * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  67.  
  68. ... optimized to ...
  69. [000006] ------------ * ADDR byref
  70. [000005] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  71.  
  72.  
  73. STMT00002 (IL 0x006... ???)
  74. [000008] ------------ * COMMA void
  75. [000006] ------------ +--* ADDR byref
  76. [000005] ------------ | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  77. [000007] ------------ \--* NOP void
  78.  
  79. [ 0] 7 (0x007) ret
  80.  
  81. STMT00003 (IL 0x007... ???)
  82. [000009] ------------ * RETURN void
  83.  
  84. *************** in fgTransformIndirectCalls(root)
  85. -- no candidates to transform
  86.  
  87. New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
  88. *************** In fgMorph()
  89. *************** In fgDebugCheckBBlist
  90. *************** In Allocate Objects
  91. Trees before Allocate Objects
  92.  
  93. -----------------------------------------------------------------------------------------------------------------------------------------
  94. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  95. -----------------------------------------------------------------------------------------------------------------------------------------
  96. BB01 [0000] 1 1 [000..008) (return) i
  97. -----------------------------------------------------------------------------------------------------------------------------------------
  98.  
  99. ------------ BB01 [000..008) (return), preds={} succs={}
  100.  
  101. ***** BB01
  102. STMT00000 (IL 0x000...0x000)
  103. [000000] ------------ * NO_OP void
  104.  
  105. ***** BB01
  106. STMT00001 (IL 0x001...0x006)
  107. [000004] -AC-G------- * ASG simd16 (copy)
  108. [000002] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  109. [000001] --C-G------- \--* CALL simd16 CoreLab.Program.Callee
  110.  
  111. ***** BB01
  112. STMT00002 (IL 0x006... ???)
  113. [000008] ------------ * COMMA void
  114. [000006] ------------ +--* ADDR byref
  115. [000005] ------------ | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  116. [000007] ------------ \--* NOP void
  117.  
  118. ***** BB01
  119. STMT00003 (IL 0x007...0x007)
  120. [000009] ------------ * RETURN void
  121.  
  122. -------------------------------------------------------------------------------------------------------------------
  123.  
  124. *** ObjectAllocationPhase: no newobjs in this method; punting
  125. *************** Exiting Allocate Objects
  126. Trees after Allocate Objects
  127.  
  128. -----------------------------------------------------------------------------------------------------------------------------------------
  129. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  130. -----------------------------------------------------------------------------------------------------------------------------------------
  131. BB01 [0000] 1 1 [000..008) (return) i
  132. -----------------------------------------------------------------------------------------------------------------------------------------
  133.  
  134. ------------ BB01 [000..008) (return), preds={} succs={}
  135.  
  136. ***** BB01
  137. STMT00000 (IL 0x000...0x000)
  138. [000000] ------------ * NO_OP void
  139.  
  140. ***** BB01
  141. STMT00001 (IL 0x001...0x006)
  142. [000004] -AC-G------- * ASG simd16 (copy)
  143. [000002] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  144. [000001] --C-G------- \--* CALL simd16 CoreLab.Program.Callee
  145.  
  146. ***** BB01
  147. STMT00002 (IL 0x006... ???)
  148. [000008] ------------ * COMMA void
  149. [000006] ------------ +--* ADDR byref
  150. [000005] ------------ | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  151. [000007] ------------ \--* NOP void
  152.  
  153. ***** BB01
  154. STMT00003 (IL 0x007...0x007)
  155. [000009] ------------ * RETURN void
  156.  
  157. -------------------------------------------------------------------------------------------------------------------
  158. New Basic Block BB02 [0001] created.
  159. New scratch BB02
  160.  
  161. *************** After fgAddInternal()
  162.  
  163. -----------------------------------------------------------------------------------------------------------------------------------------
  164. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  165. -----------------------------------------------------------------------------------------------------------------------------------------
  166. BB02 [0001] 1 1 [???..???) i internal
  167. BB01 [0000] 1 1 [000..008) (return) i
  168. -----------------------------------------------------------------------------------------------------------------------------------------
  169.  
  170. *************** Exception Handling table is empty
  171. *************** In fgDebugCheckBBlist
  172.  
  173. *************** In fgRemoveEmptyTry()
  174. No EH in this method, nothing to remove.
  175.  
  176. *************** In fgRemoveEmptyFinally()
  177. No EH in this method, nothing to remove.
  178.  
  179. *************** In fgMergeFinallyChains()
  180. No EH in this method, nothing to merge.
  181.  
  182. *************** In fgCloneFinally()
  183. No EH in this method, no cloning.
  184.  
  185. *************** In fgResetImplicitByRefRefCount()
  186. *************** In fgPromoteStructs()
  187. promotion opt flag not enabled
  188.  
  189. *************** In fgMarkAddressExposedLocals()
  190. LocalAddressVisitor visiting statement:
  191. STMT00004 (IL ???... ???)
  192. [000017] --C-G------- * QMARK void
  193. [000013] Q----------- if +--* EQ int
  194. [000011] ------------ | +--* IND int
  195. [000010] ------------ | | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  196. [000012] ------------ | \--* CNS_INT int 0
  197. [000016] --C-G------- if \--* COLON void
  198. [000014] --C-G------- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  199. [000015] ------------ then \--* NOP void
  200.  
  201. LocalAddressVisitor visiting statement:
  202. STMT00000 (IL 0x000...0x000)
  203. [000000] ------------ * NO_OP void
  204.  
  205. LocalAddressVisitor visiting statement:
  206. STMT00001 (IL 0x001...0x006)
  207. [000004] -AC-G------- * ASG simd16 (copy)
  208. [000002] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  209. [000001] --C-G------- \--* CALL simd16 CoreLab.Program.Callee
  210.  
  211. LocalAddressVisitor visiting statement:
  212. STMT00002 (IL 0x006... ???)
  213. [000008] ------------ * COMMA void
  214. [000006] ------------ +--* ADDR byref
  215. [000005] ------------ | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  216. [000007] ------------ \--* NOP void
  217.  
  218. Local V01 should not be enregistered because: it is address exposed
  219.  
  220. LocalAddressVisitor visiting statement:
  221. STMT00003 (IL 0x007...0x007)
  222. [000009] ------------ * RETURN void
  223.  
  224.  
  225. *************** In fgRetypeImplicitByRefArgs()
  226.  
  227. *************** In fgMorphBlocks()
  228.  
  229. Morphing BB02 of 'CoreLab.Program:Caller()'
  230.  
  231. fgMorphTree BB02, STMT00004 (before)
  232. [000017] --C-G------- * QMARK void
  233. [000013] Q----------- if +--* EQ int
  234. [000011] ------------ | +--* IND int
  235. [000010] ------------ | | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  236. [000012] ------------ | \--* CNS_INT int 0
  237. [000016] --C-G------- if \--* COLON void
  238. [000014] --C-G------- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  239. [000015] ------------ then \--* NOP void
  240. Initializing arg info for 14.CALL:
  241. ArgTable for 14.CALL after fgInitArgInfo:
  242.  
  243. Morphing args for 14.CALL:
  244. argSlots=0, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
  245. ArgTable for 14.CALL after fgMorphArgs:
  246.  
  247.  
  248. Morphing BB01 of 'CoreLab.Program:Caller()'
  249.  
  250. fgMorphTree BB01, STMT00000 (before)
  251. [000000] ------------ * NO_OP void
  252.  
  253. fgMorphTree BB01, STMT00001 (before)
  254. [000004] -AC-G------- * ASG simd16 (copy)
  255. [000002] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  256. [000001] --C-G------- \--* CALL simd16 CoreLab.Program.Callee
  257. Known type Vector128<double>
  258. Initializing arg info for 1.CALL:
  259. ArgTable for 1.CALL after fgInitArgInfo:
  260.  
  261. Morphing args for 1.CALL:
  262. argSlots=0, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
  263. ArgTable for 1.CALL after fgMorphArgs:
  264.  
  265.  
  266. fgMorphCopyBlock:fgMorphOneAsgBlock (after):
  267. [000004] -ACXG------- * ASG simd16 (copy)
  268. [000002] D---G+-N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  269. [000001] --CXG+------ \--* CALL simd16 CoreLab.Program.Callee
  270. using oneAsgTree.
  271.  
  272. fgMorphCopyBlock (after):
  273. [000004] -ACXG------- * ASG simd16 (copy)
  274. [000002] D---G+-N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  275. [000001] --CXG+------ \--* CALL simd16 CoreLab.Program.Callee
  276.  
  277. fgMorphTree BB01, STMT00002 (before)
  278. [000008] ------------ * COMMA void
  279. [000006] ------------ +--* ADDR byref
  280. [000005] ------------ | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  281. [000007] ------------ \--* NOP void
  282.  
  283. fgMorphTree BB01, STMT00002 (after)
  284. [000007] -----+------ * NOP void
  285.  
  286. fgMorphTree BB01, STMT00003 (before)
  287. [000009] ------------ * RETURN void
  288.  
  289. Expanding top-level qmark in BB02 (before)
  290.  
  291. -----------------------------------------------------------------------------------------------------------------------------------------
  292. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  293. -----------------------------------------------------------------------------------------------------------------------------------------
  294. BB02 [0001] 1 1 [???..???) i internal
  295. -----------------------------------------------------------------------------------------------------------------------------------------
  296.  
  297. ------------ BB02 [???..???), preds={} succs={BB01}
  298.  
  299. ***** BB02
  300. STMT00004 (IL ???... ???)
  301. [000017] --C-G+------ * QMARK void
  302. [000013] J----+-N---- if +--* EQ int
  303. [000011] n----+------ | +--* IND int
  304. [000010] -----+------ | | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  305. [000012] -----+------ | \--* CNS_INT int 0
  306. [000016] --C-G+?----- if \--* COLON void
  307. [000014] --C-G+?----- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  308. [000015] -----+?----- then \--* NOP void
  309.  
  310. -------------------------------------------------------------------------------------------------------------------
  311. New Basic Block BB03 [0002] created.
  312. BB01 previous predecessor was BB02, now is BB03
  313. New Basic Block BB04 [0003] created.
  314. New Basic Block BB05 [0004] created.
  315.  
  316. Removing statement STMT00004 (IL ???... ???)
  317. [000017] --C-G+------ * QMARK void
  318. [000013] J----+-N---- if +--* EQ int
  319. [000011] n----+------ | +--* IND int
  320. [000010] -----+------ | | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  321. [000012] -----+------ | \--* CNS_INT int 0
  322. [000016] --C-G+?----- if \--* COLON void
  323. [000014] --C-G+?----- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  324. [000015] -----+?----- then \--* NOP void
  325. in BB02 as useless:
  326.  
  327. BB02 becomes empty
  328.  
  329. Expanding top-level qmark in BB02 (after)
  330.  
  331. -----------------------------------------------------------------------------------------------------------------------------------------
  332. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  333. -----------------------------------------------------------------------------------------------------------------------------------------
  334. BB02 [0001] 1 1 [???..???) i internal
  335. BB04 [0003] 1 1 [???..???)-> BB03 ( cond ) internal
  336. BB05 [0004] 1 0.50 [???..???) internal
  337. BB03 [0002] 2 1 [???..???) i internal label target
  338. -----------------------------------------------------------------------------------------------------------------------------------------
  339.  
  340. ------------ BB02 [???..???), preds={} succs={BB04}
  341.  
  342. ------------ BB04 [???..???) -> BB03 (cond), preds={} succs={BB05,BB03}
  343.  
  344. ***** BB04
  345. STMT00005 (IL ???... ???)
  346. [000018] ------------ * JTRUE void
  347. [000013] J----+-N---- \--* EQ int
  348. [000011] n----+------ +--* IND int
  349. [000010] -----+------ | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  350. [000012] -----+------ \--* CNS_INT int 0
  351.  
  352. ------------ BB05 [???..???), preds={} succs={BB03}
  353.  
  354. ***** BB05
  355. STMT00006 (IL ???... ???)
  356. [000014] --C-G+?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  357.  
  358. ------------ BB03 [???..???), preds={} succs={BB01}
  359.  
  360. -------------------------------------------------------------------------------------------------------------------
  361.  
  362. Renumbering the basic blocks for fgComputePred
  363.  
  364. *************** Before renumbering the basic blocks
  365.  
  366. -----------------------------------------------------------------------------------------------------------------------------------------
  367. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  368. -----------------------------------------------------------------------------------------------------------------------------------------
  369. BB02 [0001] 1 1 [???..???) i internal
  370. BB04 [0003] 1 1 [???..???)-> BB03 ( cond ) internal
  371. BB05 [0004] 1 0.50 [???..???) internal
  372. BB03 [0002] 2 1 [???..???) i internal label target
  373. BB01 [0000] 1 1 [000..008) (return) i gcsafe
  374. -----------------------------------------------------------------------------------------------------------------------------------------
  375.  
  376. *************** Exception Handling table is empty
  377. Renumber BB02 to BB01
  378. Renumber BB04 to BB02
  379. Renumber BB05 to BB03
  380. Renumber BB03 to BB04
  381. Renumber BB01 to BB05
  382.  
  383. *************** After renumbering the basic blocks
  384.  
  385. -----------------------------------------------------------------------------------------------------------------------------------------
  386. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  387. -----------------------------------------------------------------------------------------------------------------------------------------
  388. BB01 [0001] 1 1 [???..???) i internal
  389. BB02 [0003] 1 1 [???..???)-> BB04 ( cond ) internal
  390. BB03 [0004] 1 0.50 [???..???) internal
  391. BB04 [0002] 2 1 [???..???) i internal label target
  392. BB05 [0000] 1 1 [000..008) (return) i gcsafe
  393. -----------------------------------------------------------------------------------------------------------------------------------------
  394.  
  395. *************** Exception Handling table is empty
  396.  
  397. New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
  398.  
  399. *************** In fgComputePreds()
  400.  
  401. -----------------------------------------------------------------------------------------------------------------------------------------
  402. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  403. -----------------------------------------------------------------------------------------------------------------------------------------
  404. BB01 [0001] 1 1 [???..???) i internal
  405. BB02 [0003] 1 1 [???..???)-> BB04 ( cond ) internal
  406. BB03 [0004] 1 0.50 [???..???) internal
  407. BB04 [0002] 2 1 [???..???) i internal label target
  408. BB05 [0000] 1 1 [000..008) (return) i gcsafe
  409. -----------------------------------------------------------------------------------------------------------------------------------------
  410.  
  411.  
  412. *************** After fgComputePreds()
  413.  
  414. -----------------------------------------------------------------------------------------------------------------------------------------
  415. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  416. -----------------------------------------------------------------------------------------------------------------------------------------
  417. BB01 [0001] 1 1 [???..???) i internal label target
  418. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  419. BB03 [0004] 1 BB02 0.50 [???..???) internal
  420. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target
  421. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe
  422. -----------------------------------------------------------------------------------------------------------------------------------------
  423.  
  424. *************** In fgComputeBlockAndEdgeWeights()
  425.  
  426. -----------------------------------------------------------------------------------------------------------------------------------------
  427. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  428. -----------------------------------------------------------------------------------------------------------------------------------------
  429. BB01 [0001] 1 1 [???..???) i internal label target
  430. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  431. BB03 [0004] 1 BB02 0.50 [???..???) internal
  432. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target
  433. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe
  434. -----------------------------------------------------------------------------------------------------------------------------------------
  435.  
  436. -- no profile data, so using default called count
  437. -- not optimizing, so not computing edge weights
  438. *************** In fgCreateFunclets()
  439.  
  440. After fgCreateFunclets()
  441. -----------------------------------------------------------------------------------------------------------------------------------------
  442. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  443. -----------------------------------------------------------------------------------------------------------------------------------------
  444. BB01 [0001] 1 1 [???..???) i internal label target
  445. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  446. BB03 [0004] 1 BB02 0.50 [???..???) internal
  447. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target
  448. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe
  449. -----------------------------------------------------------------------------------------------------------------------------------------
  450.  
  451. *************** Exception Handling table is empty
  452. *************** In fgDebugCheckBBlist
  453.  
  454. *************** In lvaMarkLocalVars()
  455. *** lvaComputeRefCounts ***
  456. *************** In fgFindOperOrder()
  457. *************** In fgSetBlockOrder()
  458. The biggest BB has 5 tree nodes
  459.  
  460. -----------------------------------------------------------------------------------------------------------------------------------------
  461. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  462. -----------------------------------------------------------------------------------------------------------------------------------------
  463. BB01 [0001] 1 1 [???..???) i internal label target
  464. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  465. BB03 [0004] 1 BB02 0.50 [???..???) internal
  466. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target
  467. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe
  468. -----------------------------------------------------------------------------------------------------------------------------------------
  469.  
  470. ------------ BB01 [???..???), preds={} succs={BB02}
  471.  
  472. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  473.  
  474. ***** BB02
  475. STMT00005 (IL ???... ???)
  476. N005 ( 9, 16) [000018] ------------ * JTRUE void
  477. N004 ( 7, 14) [000013] J------N---- \--* EQ int
  478. N002 ( 5, 12) [000011] n----------- +--* IND int
  479. N001 ( 3, 10) [000010] ------------ | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  480. N003 ( 1, 1) [000012] ------------ \--* CNS_INT int 0
  481.  
  482. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  483.  
  484. ***** BB03
  485. STMT00006 (IL ???... ???)
  486. N001 ( 14, 5) [000014] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  487.  
  488. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  489.  
  490. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  491.  
  492. ***** BB05
  493. STMT00000 (IL 0x000...0x000)
  494. N001 ( 1, 1) [000000] ------------ * NO_OP void
  495.  
  496. ***** BB05
  497. STMT00001 (IL 0x001...0x006)
  498. N003 ( 18, 8) [000004] -ACXG---R--- * ASG simd16 (copy)
  499. N002 ( 3, 2) [000002] D---G--N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  500. N001 ( 14, 5) [000001] --CXG------- \--* CALL simd16 CoreLab.Program.Callee
  501.  
  502. ***** BB05
  503. STMT00002 (IL 0x006... ???)
  504. N001 ( 0, 0) [000007] ------------ * NOP void
  505.  
  506. ***** BB05
  507. STMT00003 (IL 0x007...0x007)
  508. N001 ( 0, 0) [000009] ------------ * RETURN void
  509.  
  510. -------------------------------------------------------------------------------------------------------------------
  511.  
  512.  
  513. *************** In fgDetermineFirstColdBlock()
  514. No procedure splitting will be done for this method
  515. *************** In IR Rationalize
  516. Trees before IR Rationalize
  517.  
  518. -----------------------------------------------------------------------------------------------------------------------------------------
  519. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  520. -----------------------------------------------------------------------------------------------------------------------------------------
  521. BB01 [0001] 1 1 [???..???) i internal label target
  522. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  523. BB03 [0004] 1 BB02 0.50 [???..???) internal
  524. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target
  525. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe
  526. -----------------------------------------------------------------------------------------------------------------------------------------
  527.  
  528. ------------ BB01 [???..???), preds={} succs={BB02}
  529.  
  530. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  531.  
  532. ***** BB02
  533. STMT00005 (IL ???... ???)
  534. N005 ( 9, 16) [000018] ------------ * JTRUE void
  535. N004 ( 7, 14) [000013] J------N---- \--* EQ int
  536. N002 ( 5, 12) [000011] n----------- +--* IND int
  537. N001 ( 3, 10) [000010] ------------ | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  538. N003 ( 1, 1) [000012] ------------ \--* CNS_INT int 0
  539.  
  540. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  541.  
  542. ***** BB03
  543. STMT00006 (IL ???... ???)
  544. N001 ( 14, 5) [000014] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  545.  
  546. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  547.  
  548. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  549.  
  550. ***** BB05
  551. STMT00000 (IL 0x000...0x000)
  552. N001 ( 1, 1) [000000] ------------ * NO_OP void
  553.  
  554. ***** BB05
  555. STMT00001 (IL 0x001...0x006)
  556. N003 ( 18, 8) [000004] -ACXG---R--- * ASG simd16 (copy)
  557. N002 ( 3, 2) [000002] D---G--N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  558. N001 ( 14, 5) [000001] --CXG------- \--* CALL simd16 CoreLab.Program.Callee
  559.  
  560. ***** BB05
  561. STMT00002 (IL 0x006... ???)
  562. N001 ( 0, 0) [000007] ------------ * NOP void
  563.  
  564. ***** BB05
  565. STMT00003 (IL 0x007...0x007)
  566. N001 ( 0, 0) [000009] ------------ * RETURN void
  567.  
  568. -------------------------------------------------------------------------------------------------------------------
  569. rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
  570. N003 ( 18, 8) [000004] DACXG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  571.  
  572. *************** Exiting IR Rationalize
  573. Trees after IR Rationalize
  574.  
  575. -----------------------------------------------------------------------------------------------------------------------------------------
  576. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  577. -----------------------------------------------------------------------------------------------------------------------------------------
  578. BB01 [0001] 1 1 [???..???) i internal label target LIR
  579. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  580. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  581. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  582. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  583. -----------------------------------------------------------------------------------------------------------------------------------------
  584.  
  585. ------------ BB01 [???..???), preds={} succs={BB02}
  586.  
  587. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  588. N001 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fff4561eaf0 token
  589. /--* t10 long
  590. N002 ( 5, 12) [000011] n----------- t11 = * IND int
  591. N003 ( 1, 1) [000012] ------------ t12 = CNS_INT int 0
  592. /--* t11 int
  593. +--* t12 int
  594. N004 ( 7, 14) [000013] J------N---- t13 = * EQ int
  595. /--* t13 int
  596. N005 ( 9, 16) [000018] ------------ * JTRUE void
  597.  
  598. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  599. N001 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  600.  
  601. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  602.  
  603. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  604. [000019] ------------ IL_OFFSET void IL offset: 0x0
  605. N001 ( 1, 1) [000000] ------------ NO_OP void
  606. [000020] ------------ IL_OFFSET void IL offset: 0x1
  607. N001 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee
  608. /--* t1 simd16
  609. N003 ( 18, 8) [000004] DA-XG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  610. [000021] ------------ IL_OFFSET void IL offset: 0x6
  611. N001 ( 0, 0) [000007] ------------ NOP void
  612. [000022] ------------ IL_OFFSET void IL offset: 0x7
  613. N001 ( 0, 0) [000009] ------------ RETURN void
  614.  
  615. -------------------------------------------------------------------------------------------------------------------
  616. *************** In fgDebugCheckBBlist
  617. Bumping outgoingArgSpaceSize to 32 for call [000014]
  618. outgoingArgSpaceSize 32 sufficient for call [000001], which needs 32
  619. *************** In fgDebugCheckBBlist
  620. *************** In Lowering
  621. Trees before Lowering
  622.  
  623. -----------------------------------------------------------------------------------------------------------------------------------------
  624. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  625. -----------------------------------------------------------------------------------------------------------------------------------------
  626. BB01 [0001] 1 1 [???..???) i internal label target LIR
  627. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  628. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  629. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  630. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  631. -----------------------------------------------------------------------------------------------------------------------------------------
  632.  
  633. ------------ BB01 [???..???), preds={} succs={BB02}
  634.  
  635. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  636. N001 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fff4561eaf0 token
  637. /--* t10 long
  638. N002 ( 5, 12) [000011] n----------- t11 = * IND int
  639. N003 ( 1, 1) [000012] ------------ t12 = CNS_INT int 0
  640. /--* t11 int
  641. +--* t12 int
  642. N004 ( 7, 14) [000013] J------N---- t13 = * EQ int
  643. /--* t13 int
  644. N005 ( 9, 16) [000018] ------------ * JTRUE void
  645.  
  646. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  647. N001 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  648.  
  649. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  650.  
  651. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  652. [000019] ------------ IL_OFFSET void IL offset: 0x0
  653. N001 ( 1, 1) [000000] ------------ NO_OP void
  654. [000020] ------------ IL_OFFSET void IL offset: 0x1
  655. N001 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee
  656. /--* t1 simd16
  657. N003 ( 18, 8) [000004] DA-XG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  658. [000021] ------------ IL_OFFSET void IL offset: 0x6
  659. N001 ( 0, 0) [000007] ------------ NOP void
  660. [000022] ------------ IL_OFFSET void IL offset: 0x7
  661. N001 ( 0, 0) [000009] ------------ RETURN void
  662.  
  663. -------------------------------------------------------------------------------------------------------------------
  664. lowering call (before):
  665. N001 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  666.  
  667. objp:
  668. ======
  669.  
  670. args:
  671. ======
  672.  
  673. late:
  674. ======
  675. lowering call (after):
  676. N001 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  677.  
  678. lowering call (before):
  679. N001 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee
  680.  
  681. objp:
  682. ======
  683.  
  684. args:
  685. ======
  686.  
  687. late:
  688. ======
  689. lowering call (after):
  690. N001 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee
  691.  
  692. lowering GT_RETURN
  693. N001 ( 0, 0) [000009] ------------ * RETURN void
  694. ============Lower has completed modifying nodes.
  695.  
  696. -----------------------------------------------------------------------------------------------------------------------------------------
  697. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  698. -----------------------------------------------------------------------------------------------------------------------------------------
  699. BB01 [0001] 1 1 [???..???) i internal label target LIR
  700. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  701. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  702. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  703. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  704. -----------------------------------------------------------------------------------------------------------------------------------------
  705.  
  706. ------------ BB01 [???..???), preds={} succs={BB02}
  707.  
  708. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  709. N001 ( 3, 10) [000010] -c---------- t10 = CNS_INT(h) long 0x7fff4561eaf0 token
  710. /--* t10 long
  711. N002 ( 5, 12) [000011] nc---------- t11 = * IND int
  712. N003 ( 1, 1) [000012] -c---------- t12 = CNS_INT int 0
  713. /--* t11 int
  714. +--* t12 int
  715. N004 ( 7, 14) [000013] J------N---- * EQ void
  716. N005 ( 9, 16) [000018] ------------ * JTRUE void
  717.  
  718. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  719. N001 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  720.  
  721. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  722.  
  723. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  724. [000019] ------------ IL_OFFSET void IL offset: 0x0
  725. N001 ( 1, 1) [000000] ------------ NO_OP void
  726. [000020] ------------ IL_OFFSET void IL offset: 0x1
  727. N001 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee
  728. /--* t1 simd16
  729. N003 ( 18, 8) [000004] DA-XG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  730. [000021] ------------ IL_OFFSET void IL offset: 0x6
  731. N001 ( 0, 0) [000007] ------------ NOP void
  732. [000022] ------------ IL_OFFSET void IL offset: 0x7
  733. N001 ( 0, 0) [000009] ------------ RETURN void
  734.  
  735. -------------------------------------------------------------------------------------------------------------------
  736.  
  737. *** lvaComputeRefCounts ***
  738. *************** In fgLocalVarLiveness()
  739. ; Initial local variable assignments
  740. ;
  741. ; V00 OutArgs lclBlk (32) "OutgoingArgSpace"
  742. ; V01 tmp1 simd16 do-not-enreg[XS] addr-exposed "impSpillStackEnsure"
  743. In fgLocalVarLivenessInit
  744. *************** In fgPerBlockLocalVarLiveness()
  745. *************** In fgInterBlockLocalVarLiveness()
  746.  
  747. *** lvaComputeRefCounts ***
  748. Liveness pass finished after lowering, IR:
  749.  
  750. -----------------------------------------------------------------------------------------------------------------------------------------
  751. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  752. -----------------------------------------------------------------------------------------------------------------------------------------
  753. BB01 [0001] 1 1 [???..???) i internal label target LIR
  754. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  755. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  756. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  757. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  758. -----------------------------------------------------------------------------------------------------------------------------------------
  759.  
  760. ------------ BB01 [???..???), preds={} succs={BB02}
  761.  
  762. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  763. N001 ( 3, 10) [000010] -c---------- t10 = CNS_INT(h) long 0x7fff4561eaf0 token
  764. /--* t10 long
  765. N002 ( 5, 12) [000011] nc---------- t11 = * IND int
  766. N003 ( 1, 1) [000012] -c---------- t12 = CNS_INT int 0
  767. /--* t11 int
  768. +--* t12 int
  769. N004 ( 7, 14) [000013] J------N---- * EQ void
  770. N005 ( 9, 16) [000018] ------------ * JTRUE void
  771.  
  772. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  773. N001 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  774.  
  775. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  776.  
  777. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  778. [000019] ------------ IL_OFFSET void IL offset: 0x0
  779. N001 ( 1, 1) [000000] ------------ NO_OP void
  780. [000020] ------------ IL_OFFSET void IL offset: 0x1
  781. N001 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee
  782. /--* t1 simd16
  783. N003 ( 18, 8) [000004] DA-XG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  784. [000021] ------------ IL_OFFSET void IL offset: 0x6
  785. N001 ( 0, 0) [000007] ------------ NOP void
  786. [000022] ------------ IL_OFFSET void IL offset: 0x7
  787. N001 ( 0, 0) [000009] ------------ RETURN void
  788.  
  789. -------------------------------------------------------------------------------------------------------------------
  790. *************** Exiting Lowering
  791. Trees after Lowering
  792.  
  793. -----------------------------------------------------------------------------------------------------------------------------------------
  794. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  795. -----------------------------------------------------------------------------------------------------------------------------------------
  796. BB01 [0001] 1 1 [???..???) i internal label target LIR
  797. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  798. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  799. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  800. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  801. -----------------------------------------------------------------------------------------------------------------------------------------
  802.  
  803. ------------ BB01 [???..???), preds={} succs={BB02}
  804.  
  805. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  806. N001 ( 3, 10) [000010] -c---------- t10 = CNS_INT(h) long 0x7fff4561eaf0 token
  807. /--* t10 long
  808. N002 ( 5, 12) [000011] nc---------- t11 = * IND int
  809. N003 ( 1, 1) [000012] -c---------- t12 = CNS_INT int 0
  810. /--* t11 int
  811. +--* t12 int
  812. N004 ( 7, 14) [000013] J------N---- * EQ void
  813. N005 ( 9, 16) [000018] ------------ * JTRUE void
  814.  
  815. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  816. N001 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  817.  
  818. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  819.  
  820. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  821. [000019] ------------ IL_OFFSET void IL offset: 0x0
  822. N001 ( 1, 1) [000000] ------------ NO_OP void
  823. [000020] ------------ IL_OFFSET void IL offset: 0x1
  824. N001 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee
  825. /--* t1 simd16
  826. N003 ( 18, 8) [000004] DA-XG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  827. [000021] ------------ IL_OFFSET void IL offset: 0x6
  828. N001 ( 0, 0) [000007] ------------ NOP void
  829. [000022] ------------ IL_OFFSET void IL offset: 0x7
  830. N001 ( 0, 0) [000009] ------------ RETURN void
  831.  
  832. -------------------------------------------------------------------------------------------------------------------
  833. *************** In fgDebugCheckBBlist
  834. *************** In StackLevelSetter
  835. Trees before StackLevelSetter
  836.  
  837. -----------------------------------------------------------------------------------------------------------------------------------------
  838. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  839. -----------------------------------------------------------------------------------------------------------------------------------------
  840. BB01 [0001] 1 1 [???..???) i internal label target LIR
  841. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  842. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  843. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  844. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  845. -----------------------------------------------------------------------------------------------------------------------------------------
  846.  
  847. ------------ BB01 [???..???), preds={} succs={BB02}
  848.  
  849. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  850. N001 ( 3, 10) [000010] -c---------- t10 = CNS_INT(h) long 0x7fff4561eaf0 token
  851. /--* t10 long
  852. N002 ( 5, 12) [000011] nc---------- t11 = * IND int
  853. N003 ( 1, 1) [000012] -c---------- t12 = CNS_INT int 0
  854. /--* t11 int
  855. +--* t12 int
  856. N004 ( 7, 14) [000013] J------N---- * EQ void
  857. N005 ( 9, 16) [000018] ------------ * JTRUE void
  858.  
  859. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  860. N001 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  861.  
  862. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  863.  
  864. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  865. [000019] ------------ IL_OFFSET void IL offset: 0x0
  866. N001 ( 1, 1) [000000] ------------ NO_OP void
  867. [000020] ------------ IL_OFFSET void IL offset: 0x1
  868. N001 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee
  869. /--* t1 simd16
  870. N003 ( 18, 8) [000004] DA-XG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  871. [000021] ------------ IL_OFFSET void IL offset: 0x6
  872. N001 ( 0, 0) [000007] ------------ NOP void
  873. [000022] ------------ IL_OFFSET void IL offset: 0x7
  874. N001 ( 0, 0) [000009] ------------ RETURN void
  875.  
  876. -------------------------------------------------------------------------------------------------------------------
  877. *************** Exiting StackLevelSetter
  878. Trees after StackLevelSetter
  879.  
  880. -----------------------------------------------------------------------------------------------------------------------------------------
  881. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  882. -----------------------------------------------------------------------------------------------------------------------------------------
  883. BB01 [0001] 1 1 [???..???) i internal label target LIR
  884. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  885. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  886. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  887. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  888. -----------------------------------------------------------------------------------------------------------------------------------------
  889.  
  890. ------------ BB01 [???..???), preds={} succs={BB02}
  891.  
  892. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  893. N001 ( 3, 10) [000010] -c---------- t10 = CNS_INT(h) long 0x7fff4561eaf0 token
  894. /--* t10 long
  895. N002 ( 5, 12) [000011] nc---------- t11 = * IND int
  896. N003 ( 1, 1) [000012] -c---------- t12 = CNS_INT int 0
  897. /--* t11 int
  898. +--* t12 int
  899. N004 ( 7, 14) [000013] J------N---- * EQ void
  900. N005 ( 9, 16) [000018] ------------ * JTRUE void
  901.  
  902. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  903. N001 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  904.  
  905. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  906.  
  907. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  908. [000019] ------------ IL_OFFSET void IL offset: 0x0
  909. N001 ( 1, 1) [000000] ------------ NO_OP void
  910. [000020] ------------ IL_OFFSET void IL offset: 0x1
  911. N001 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee
  912. /--* t1 simd16
  913. N003 ( 18, 8) [000004] DA-XG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  914. [000021] ------------ IL_OFFSET void IL offset: 0x6
  915. N001 ( 0, 0) [000007] ------------ NOP void
  916. [000022] ------------ IL_OFFSET void IL offset: 0x7
  917. N001 ( 0, 0) [000009] ------------ RETURN void
  918.  
  919. -------------------------------------------------------------------------------------------------------------------
  920. *************** In fgDebugCheckBBlist
  921. Clearing modified regs.
  922.  
  923. buildIntervals ========
  924.  
  925. -----------------
  926. LIVENESS:
  927. -----------------
  928. BB01 use def in out
  929. {}
  930. {}
  931. {}
  932. {}
  933. BB02 use def in out
  934. {}
  935. {}
  936. {}
  937. {}
  938. BB03 use def in out
  939. {}
  940. {}
  941. {}
  942. {}
  943. BB04 use def in out
  944. {}
  945. {}
  946. {}
  947. {}
  948. BB05 use def in out
  949. {}
  950. {}
  951. {}
  952. {}
  953.  
  954. FP callee save candidate vars: None
  955.  
  956. floatVarCount = 0; hasLoops = 0, singleExit = 1
  957. TUPLE STYLE DUMP BEFORE LSRA
  958. LSRA Block Sequence: BB01( 1 )
  959. BB02( 1 )
  960. BB03( 0.50)
  961. BB04( 1 )
  962. BB05( 1 )
  963.  
  964. BB01 [???..???), preds={} succs={BB02}
  965. =====
  966.  
  967. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  968. =====
  969. N001. CNS_INT(h) 0x7fff4561eaf0 token
  970. N002. IND
  971. N003. CNS_INT 0
  972. N004. EQ
  973. N005. JTRUE
  974.  
  975. BB03 [???..???), preds={BB02} succs={BB04}
  976. =====
  977. N001. CALL help
  978.  
  979. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  980. =====
  981.  
  982. BB05 [000..008) (return), preds={BB04} succs={}
  983. =====
  984. N000. IL_OFFSET IL offset: 0x0
  985. N001. NO_OP
  986. N000. IL_OFFSET IL offset: 0x1
  987. N001. t1 = CALL
  988. N003. V01 MEM; t1
  989. N000. IL_OFFSET IL offset: 0x6
  990. N001. NOP
  991. N000. IL_OFFSET IL offset: 0x7
  992. N001. RETURN
  993.  
  994.  
  995.  
  996.  
  997. buildIntervals second part ========
  998.  
  999. NEW BLOCK BB01
  1000. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  1001.  
  1002.  
  1003. NEW BLOCK BB02
  1004.  
  1005.  
  1006. Setting BB01 as the predecessor for determining incoming variable registers of BB02
  1007. <RefPosition #1 @2 RefTypeBB BB02 regmask=[] minReg=1>
  1008.  
  1009. DefList: { }
  1010. N004 ( 3, 10) [000010] -c---------- * CNS_INT(h) long 0x7fff4561eaf0 token REG NA
  1011. Contained
  1012. DefList: { }
  1013. N006 ( 5, 12) [000011] nc---------- * IND int REG NA
  1014. Contained
  1015. DefList: { }
  1016. N008 ( 1, 1) [000012] -c---------- * CNS_INT int 0 REG NA
  1017. Contained
  1018. DefList: { }
  1019. N010 ( 7, 14) [000013] J------N---- * EQ void REG NA
  1020.  
  1021. DefList: { }
  1022. N012 ( 9, 16) [000018] ------------ * JTRUE void REG NA
  1023.  
  1024.  
  1025. NEW BLOCK BB03
  1026.  
  1027.  
  1028. Setting BB02 as the predecessor for determining incoming variable registers of BB03
  1029. <RefPosition #2 @14 RefTypeBB BB03 regmask=[] minReg=1>
  1030.  
  1031. DefList: { }
  1032. N016 ( 14, 5) [000014] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  1033. <RefPosition #3 @17 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1>
  1034. <RefPosition #4 @17 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1>
  1035. <RefPosition #5 @17 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1>
  1036. <RefPosition #6 @17 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1>
  1037. <RefPosition #7 @17 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1>
  1038. <RefPosition #8 @17 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1>
  1039. <RefPosition #9 @17 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1>
  1040. <RefPosition #10 @17 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1>
  1041. <RefPosition #11 @17 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1>
  1042. <RefPosition #12 @17 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1>
  1043. <RefPosition #13 @17 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1>
  1044. <RefPosition #14 @17 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1>
  1045. <RefPosition #15 @17 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1>
  1046.  
  1047.  
  1048. NEW BLOCK BB04
  1049.  
  1050.  
  1051. Setting BB02 as the predecessor for determining incoming variable registers of BB04
  1052. <RefPosition #16 @18 RefTypeBB BB04 regmask=[] minReg=1>
  1053.  
  1054.  
  1055. NEW BLOCK BB05
  1056.  
  1057.  
  1058. Setting BB04 as the predecessor for determining incoming variable registers of BB05
  1059. <RefPosition #17 @20 RefTypeBB BB05 regmask=[] minReg=1>
  1060.  
  1061. DefList: { }
  1062. N022 (???,???) [000019] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
  1063.  
  1064. DefList: { }
  1065. N024 ( 1, 1) [000000] ------------ * NO_OP void REG NA
  1066.  
  1067. DefList: { }
  1068. N026 (???,???) [000020] ------------ * IL_OFFSET void IL offset: 0x1 REG NA
  1069.  
  1070. DefList: { }
  1071. N028 ( 14, 5) [000001] --CXG------- * CALL simd16 CoreLab.Program.Callee REG NA
  1072. <RefPosition #18 @29 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1>
  1073. <RefPosition #19 @29 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1074. <RefPosition #20 @29 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1>
  1075. <RefPosition #21 @29 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1>
  1076. <RefPosition #22 @29 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1>
  1077. <RefPosition #23 @29 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1>
  1078. <RefPosition #24 @29 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1>
  1079. <RefPosition #25 @29 RefTypeKill <Reg:mm0> BB05 regmask=[mm0] minReg=1>
  1080. <RefPosition #26 @29 RefTypeKill <Reg:mm1> BB05 regmask=[mm1] minReg=1>
  1081. <RefPosition #27 @29 RefTypeKill <Reg:mm2> BB05 regmask=[mm2] minReg=1>
  1082. <RefPosition #28 @29 RefTypeKill <Reg:mm3> BB05 regmask=[mm3] minReg=1>
  1083. <RefPosition #29 @29 RefTypeKill <Reg:mm4> BB05 regmask=[mm4] minReg=1>
  1084. <RefPosition #30 @29 RefTypeKill <Reg:mm5> BB05 regmask=[mm5] minReg=1>
  1085. Interval 0: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
  1086. <RefPosition #31 @29 RefTypeFixedReg <Reg:mm0> BB05 regmask=[mm0] minReg=1>
  1087. <RefPosition #32 @29 RefTypeDef <Ivl:0> CALL BB05 regmask=[mm0] minReg=1 fixed>
  1088.  
  1089. DefList: { N028.t1. CALL }
  1090. N030 ( 18, 8) [000004] DA-XG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1 NA REG NA
  1091. <RefPosition #33 @30 RefTypeUse <Ivl:0> BB05 regmask=[allFloat] minReg=1 last>
  1092.  
  1093. DefList: { }
  1094. N032 (???,???) [000021] ------------ * IL_OFFSET void IL offset: 0x6 REG NA
  1095.  
  1096. DefList: { }
  1097. N034 ( 0, 0) [000007] ------------ * NOP void REG NA
  1098.  
  1099. DefList: { }
  1100. N036 (???,???) [000022] ------------ * IL_OFFSET void IL offset: 0x7 REG NA
  1101.  
  1102. DefList: { }
  1103. N038 ( 0, 0) [000009] ------------ * RETURN void REG NA
  1104.  
  1105.  
  1106. Linear scan intervals BEFORE VALIDATING INTERVALS:
  1107. Interval 0: simd16 RefPositions {#32@29 #33@30} physReg:NA Preferences=[mm0]
  1108.  
  1109. ------------
  1110. REFPOSITIONS BEFORE VALIDATING INTERVALS:
  1111. ------------
  1112. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  1113. <RefPosition #1 @2 RefTypeBB BB02 regmask=[] minReg=1>
  1114. <RefPosition #2 @14 RefTypeBB BB03 regmask=[] minReg=1>
  1115. <RefPosition #3 @17 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  1116. <RefPosition #4 @17 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  1117. <RefPosition #5 @17 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  1118. <RefPosition #6 @17 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  1119. <RefPosition #7 @17 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  1120. <RefPosition #8 @17 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  1121. <RefPosition #9 @17 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  1122. <RefPosition #10 @17 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  1123. <RefPosition #11 @17 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  1124. <RefPosition #12 @17 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  1125. <RefPosition #13 @17 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  1126. <RefPosition #14 @17 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  1127. <RefPosition #15 @17 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  1128. <RefPosition #16 @18 RefTypeBB BB04 regmask=[] minReg=1>
  1129. <RefPosition #17 @20 RefTypeBB BB05 regmask=[] minReg=1>
  1130. <RefPosition #18 @29 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
  1131. <RefPosition #19 @29 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
  1132. <RefPosition #20 @29 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
  1133. <RefPosition #21 @29 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
  1134. <RefPosition #22 @29 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
  1135. <RefPosition #23 @29 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
  1136. <RefPosition #24 @29 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
  1137. <RefPosition #25 @29 RefTypeKill <Reg:mm0> BB05 regmask=[mm0] minReg=1 last>
  1138. <RefPosition #26 @29 RefTypeKill <Reg:mm1> BB05 regmask=[mm1] minReg=1 last>
  1139. <RefPosition #27 @29 RefTypeKill <Reg:mm2> BB05 regmask=[mm2] minReg=1 last>
  1140. <RefPosition #28 @29 RefTypeKill <Reg:mm3> BB05 regmask=[mm3] minReg=1 last>
  1141. <RefPosition #29 @29 RefTypeKill <Reg:mm4> BB05 regmask=[mm4] minReg=1 last>
  1142. <RefPosition #30 @29 RefTypeKill <Reg:mm5> BB05 regmask=[mm5] minReg=1 last>
  1143. <RefPosition #31 @29 RefTypeFixedReg <Reg:mm0> BB05 regmask=[mm0] minReg=1>
  1144. <RefPosition #32 @29 RefTypeDef <Ivl:0> CALL BB05 regmask=[mm0] minReg=1 fixed>
  1145. <RefPosition #33 @30 RefTypeUse <Ivl:0> BB05 regmask=[allFloat] minReg=1 last>
  1146. TUPLE STYLE DUMP WITH REF POSITIONS
  1147. Incoming Parameters:
  1148. BB01 [???..???), preds={} succs={BB02}
  1149. =====
  1150.  
  1151. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  1152. =====
  1153. N004. CNS_INT(h) 0x7fff4561eaf0 token
  1154. N006. IND
  1155. N008. CNS_INT 0
  1156. N010. EQ
  1157. N012. JTRUE
  1158.  
  1159. BB03 [???..???), preds={BB02} succs={BB04}
  1160. =====
  1161. N016. CALL help
  1162. Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5
  1163.  
  1164. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  1165. =====
  1166.  
  1167. BB05 [000..008) (return), preds={BB04} succs={}
  1168. =====
  1169. N022. IL_OFFSET IL offset: 0x0
  1170. N024. NO_OP
  1171. N026. IL_OFFSET IL offset: 0x1
  1172. N028. CALL
  1173. Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5
  1174. Def:<I0>(#32) mm0
  1175. N030. V01 MEM
  1176. Use:<I0>(#33) *
  1177. N032. IL_OFFSET IL offset: 0x6
  1178. N034. NOP
  1179. N036. IL_OFFSET IL offset: 0x7
  1180. N038. RETURN
  1181.  
  1182.  
  1183.  
  1184.  
  1185. Linear scan intervals after buildIntervals:
  1186. Interval 0: simd16 RefPositions {#32@29 #33@30} physReg:NA Preferences=[mm0]
  1187.  
  1188. *************** In LinearScan::allocateRegisters()
  1189.  
  1190. Linear scan intervals before allocateRegisters:
  1191. Interval 0: simd16 RefPositions {#32@29 #33@30} physReg:NA Preferences=[mm0]
  1192.  
  1193. ------------
  1194. REFPOSITIONS BEFORE ALLOCATION:
  1195. ------------
  1196. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  1197. <RefPosition #1 @2 RefTypeBB BB02 regmask=[] minReg=1>
  1198. <RefPosition #2 @14 RefTypeBB BB03 regmask=[] minReg=1>
  1199. <RefPosition #3 @17 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  1200. <RefPosition #4 @17 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  1201. <RefPosition #5 @17 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  1202. <RefPosition #6 @17 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  1203. <RefPosition #7 @17 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  1204. <RefPosition #8 @17 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  1205. <RefPosition #9 @17 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  1206. <RefPosition #10 @17 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  1207. <RefPosition #11 @17 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  1208. <RefPosition #12 @17 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  1209. <RefPosition #13 @17 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  1210. <RefPosition #14 @17 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  1211. <RefPosition #15 @17 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  1212. <RefPosition #16 @18 RefTypeBB BB04 regmask=[] minReg=1>
  1213. <RefPosition #17 @20 RefTypeBB BB05 regmask=[] minReg=1>
  1214. <RefPosition #18 @29 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
  1215. <RefPosition #19 @29 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
  1216. <RefPosition #20 @29 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
  1217. <RefPosition #21 @29 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
  1218. <RefPosition #22 @29 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
  1219. <RefPosition #23 @29 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
  1220. <RefPosition #24 @29 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
  1221. <RefPosition #25 @29 RefTypeKill <Reg:mm0> BB05 regmask=[mm0] minReg=1 last>
  1222. <RefPosition #26 @29 RefTypeKill <Reg:mm1> BB05 regmask=[mm1] minReg=1 last>
  1223. <RefPosition #27 @29 RefTypeKill <Reg:mm2> BB05 regmask=[mm2] minReg=1 last>
  1224. <RefPosition #28 @29 RefTypeKill <Reg:mm3> BB05 regmask=[mm3] minReg=1 last>
  1225. <RefPosition #29 @29 RefTypeKill <Reg:mm4> BB05 regmask=[mm4] minReg=1 last>
  1226. <RefPosition #30 @29 RefTypeKill <Reg:mm5> BB05 regmask=[mm5] minReg=1 last>
  1227. <RefPosition #31 @29 RefTypeFixedReg <Reg:mm0> BB05 regmask=[mm0] minReg=1>
  1228. <RefPosition #32 @29 RefTypeDef <Ivl:0> CALL BB05 regmask=[mm0] minReg=1 fixed>
  1229. <RefPosition #33 @30 RefTypeUse <Ivl:0> BB05 regmask=[allFloat] minReg=1 last>
  1230.  
  1231.  
  1232. Allocating Registers
  1233. --------------------
  1234. The following table has one or more rows for each RefPosition that is handled during allocation.
  1235. The first column provides the basic information about the RefPosition, with its type (e.g. Def,
  1236. Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
  1237. action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
  1238. The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
  1239. active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
  1240. Columns are only printed up to the last modifed register, which may increase during allocation,
  1241. in which case additional columns will appear.
  1242. Registers which are not marked modified have ---- in their column.
  1243.  
  1244. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1245. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1246. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1247. | | | | | | | | | | | | | | |
  1248. 0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
  1249. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1250. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1251. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1252. 2.#1 BB2 PredBB1 | | | | | | | | | | | | | | |
  1253. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1254. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1255. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1256. 14.#2 BB3 PredBB2 | | | | | | | | | | | | | | |
  1257. 17.#3 rax Kill Keep rax | | | | | | | | | | | | | | |
  1258. 17.#4 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  1259. 17.#5 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  1260. 17.#6 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  1261. 17.#7 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  1262. 17.#8 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  1263. 17.#9 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  1264. 17.#10 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  1265. 17.#11 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  1266. 17.#12 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  1267. 17.#13 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  1268. 17.#14 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  1269. 17.#15 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  1270. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1271. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1272. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1273. 18.#16 BB4 PredBB2 | | | | | | | | | | | | | | |
  1274. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1275. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1276. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1277. 20.#17 BB5 PredBB4 | | | | | | | | | | | | | | |
  1278. 29.#18 rax Kill Keep rax | | | | | | | | | | | | | | |
  1279. 29.#19 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  1280. 29.#20 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  1281. 29.#21 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  1282. 29.#22 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  1283. 29.#23 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  1284. 29.#24 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  1285. 29.#25 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  1286. 29.#26 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  1287. 29.#27 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  1288. 29.#28 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  1289. 29.#29 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  1290. 29.#30 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  1291. 29.#31 mm0 Fixd Keep mm0 | | | | | | | | | | | | | | |
  1292. 29.#32 I0 Def Alloc mm0 | | | | | | | | | |I0 a| | | | |
  1293. 30.#33 I0 Use * Keep mm0 | | | | | | | | | | | | | | |
  1294.  
  1295. ------------
  1296. REFPOSITIONS AFTER ALLOCATION:
  1297. ------------
  1298. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  1299. <RefPosition #1 @2 RefTypeBB BB02 regmask=[] minReg=1>
  1300. <RefPosition #2 @14 RefTypeBB BB03 regmask=[] minReg=1>
  1301. <RefPosition #3 @17 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  1302. <RefPosition #4 @17 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  1303. <RefPosition #5 @17 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  1304. <RefPosition #6 @17 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  1305. <RefPosition #7 @17 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  1306. <RefPosition #8 @17 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  1307. <RefPosition #9 @17 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  1308. <RefPosition #10 @17 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  1309. <RefPosition #11 @17 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  1310. <RefPosition #12 @17 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  1311. <RefPosition #13 @17 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  1312. <RefPosition #14 @17 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  1313. <RefPosition #15 @17 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  1314. <RefPosition #16 @18 RefTypeBB BB04 regmask=[] minReg=1>
  1315. <RefPosition #17 @20 RefTypeBB BB05 regmask=[] minReg=1>
  1316. <RefPosition #18 @29 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
  1317. <RefPosition #19 @29 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
  1318. <RefPosition #20 @29 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
  1319. <RefPosition #21 @29 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
  1320. <RefPosition #22 @29 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
  1321. <RefPosition #23 @29 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
  1322. <RefPosition #24 @29 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
  1323. <RefPosition #25 @29 RefTypeKill <Reg:mm0> BB05 regmask=[mm0] minReg=1 last>
  1324. <RefPosition #26 @29 RefTypeKill <Reg:mm1> BB05 regmask=[mm1] minReg=1 last>
  1325. <RefPosition #27 @29 RefTypeKill <Reg:mm2> BB05 regmask=[mm2] minReg=1 last>
  1326. <RefPosition #28 @29 RefTypeKill <Reg:mm3> BB05 regmask=[mm3] minReg=1 last>
  1327. <RefPosition #29 @29 RefTypeKill <Reg:mm4> BB05 regmask=[mm4] minReg=1 last>
  1328. <RefPosition #30 @29 RefTypeKill <Reg:mm5> BB05 regmask=[mm5] minReg=1 last>
  1329. <RefPosition #31 @29 RefTypeFixedReg <Reg:mm0> BB05 regmask=[mm0] minReg=1>
  1330. <RefPosition #32 @29 RefTypeDef <Ivl:0> CALL BB05 regmask=[mm0] minReg=1 fixed>
  1331. <RefPosition #33 @30 RefTypeUse <Ivl:0> BB05 regmask=[mm0] minReg=1 last>
  1332. Active intervals at end of allocation:
  1333.  
  1334. Trees after linear scan register allocator (LSRA)
  1335.  
  1336. -----------------------------------------------------------------------------------------------------------------------------------------
  1337. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  1338. -----------------------------------------------------------------------------------------------------------------------------------------
  1339. BB01 [0001] 1 1 [???..???) i internal label target LIR
  1340. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  1341. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  1342. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  1343. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  1344. -----------------------------------------------------------------------------------------------------------------------------------------
  1345.  
  1346. ------------ BB01 [???..???), preds={} succs={BB02}
  1347.  
  1348. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  1349. N004 ( 3, 10) [000010] -c---------- t10 = CNS_INT(h) long 0x7fff4561eaf0 token REG NA
  1350. /--* t10 long
  1351. N006 ( 5, 12) [000011] nc---------- t11 = * IND int REG NA
  1352. N008 ( 1, 1) [000012] -c---------- t12 = CNS_INT int 0 REG NA
  1353. /--* t11 int
  1354. +--* t12 int
  1355. N010 ( 7, 14) [000013] J------N---- * EQ void REG NA
  1356. N012 ( 9, 16) [000018] ------------ * JTRUE void REG NA
  1357.  
  1358. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  1359. N016 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  1360.  
  1361. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  1362.  
  1363. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  1364. N022 (???,???) [000019] ------------ IL_OFFSET void IL offset: 0x0 REG NA
  1365. N024 ( 1, 1) [000000] ------------ NO_OP void REG NA
  1366. N026 (???,???) [000020] ------------ IL_OFFSET void IL offset: 0x1 REG NA
  1367. N028 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee REG mm0
  1368. /--* t1 simd16
  1369. N030 ( 18, 8) [000004] DA-XG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1 NA REG NA
  1370. N032 (???,???) [000021] ------------ IL_OFFSET void IL offset: 0x6 REG NA
  1371. N034 ( 0, 0) [000007] ------------ NOP void REG NA
  1372. N036 (???,???) [000022] ------------ IL_OFFSET void IL offset: 0x7 REG NA
  1373. N038 ( 0, 0) [000009] ------------ RETURN void REG NA
  1374.  
  1375. -------------------------------------------------------------------------------------------------------------------
  1376.  
  1377. Final allocation
  1378. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1379. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1380. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1381. 0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
  1382. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1383. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1384. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1385. 2.#1 BB2 PredBB1 | | | | | | | | | | | | | | |
  1386. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1387. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1388. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1389. 14.#2 BB3 PredBB2 | | | | | | | | | | | | | | |
  1390. 17.#3 rax Kill Keep rax | | | | | | | | | | | | | | |
  1391. 17.#4 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  1392. 17.#5 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  1393. 17.#6 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  1394. 17.#7 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  1395. 17.#8 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  1396. 17.#9 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  1397. 17.#10 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  1398. 17.#11 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  1399. 17.#12 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  1400. 17.#13 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  1401. 17.#14 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  1402. 17.#15 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  1403. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1404. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1405. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1406. 18.#16 BB4 PredBB2 | | | | | | | | | | | | | | |
  1407. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1408. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1409. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1410. 20.#17 BB5 PredBB4 | | | | | | | | | | | | | | |
  1411. 29.#18 rax Kill Keep rax | | | | | | | | | | | | | | |
  1412. 29.#19 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  1413. 29.#20 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  1414. 29.#21 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  1415. 29.#22 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  1416. 29.#23 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  1417. 29.#24 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  1418. 29.#25 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  1419. 29.#26 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  1420. 29.#27 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  1421. 29.#28 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  1422. 29.#29 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  1423. 29.#30 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  1424. 29.#31 mm0 Fixd Keep mm0 | | | | | | | | | | | | | | |
  1425. 29.#32 I0 Def Alloc mm0 | | | | | | | | | |I0 a| | | | |
  1426. 30.#33 I0 Use * Keep mm0 | | | | | | | | | |I0 i| | | | |
  1427.  
  1428. Recording the maximum number of concurrent spills:
  1429.  
  1430. ----------
  1431. LSRA Stats
  1432. ----------
  1433. Total Tracked Vars: 0
  1434. Total Reg Cand Vars: 0
  1435. Total number of Intervals: 0
  1436. Total number of RefPositions: 33
  1437. Total Spill Count: 0 Weighted: 0
  1438. Total CopyReg Count: 0 Weighted: 0
  1439. Total ResolutionMov Count: 0 Weighted: 0
  1440. Total number of split edges: 0
  1441. Total Number of spill temps created: 0
  1442.  
  1443. TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
  1444. Incoming Parameters:
  1445. BB01 [???..???), preds={} succs={BB02}
  1446. =====
  1447.  
  1448. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  1449. =====
  1450. N004. CNS_INT(h) 0x7fff4561eaf0 token
  1451. N006. IND
  1452. N008. CNS_INT 0
  1453. N010. EQ
  1454. N012. JTRUE
  1455.  
  1456. BB03 [???..???), preds={BB02} succs={BB04}
  1457. =====
  1458. N016. CALL help
  1459.  
  1460. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  1461. =====
  1462.  
  1463. BB05 [000..008) (return), preds={BB04} succs={}
  1464. =====
  1465. N022. IL_OFFSET IL offset: 0x0
  1466. N024. NO_OP
  1467. N026. IL_OFFSET IL offset: 0x1
  1468. N028. mm0 = CALL
  1469. N030. V01 MEM; mm0
  1470. N032. IL_OFFSET IL offset: 0x6
  1471. N034. NOP
  1472. N036. IL_OFFSET IL offset: 0x7
  1473. N038. RETURN
  1474.  
  1475.  
  1476.  
  1477. *************** In genGenerateCode()
  1478.  
  1479. -----------------------------------------------------------------------------------------------------------------------------------------
  1480. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  1481. -----------------------------------------------------------------------------------------------------------------------------------------
  1482. BB01 [0001] 1 1 [???..???) i internal label target LIR
  1483. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  1484. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  1485. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  1486. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  1487. -----------------------------------------------------------------------------------------------------------------------------------------
  1488. *************** In fgDebugCheckBBlist
  1489. Finalizing stack frame
  1490. Modified regs: [rax rcx rdx r8-r11 mm0-mm5]
  1491. Callee-saved registers pushed: 0 []
  1492. *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
  1493. Pad V01 tmp1, size=16, stkOffs=-0x10, pad=0
  1494. Assign V01 tmp1, size=16, stkOffs=-0x20
  1495. Assign V00 OutArgs, size=32, stkOffs=-0x40
  1496. ; Final local variable assignments
  1497. ;
  1498. ; V00 OutArgs [V00 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
  1499. ; V01 tmp1 [V01 ] ( 1, 1 ) simd16 -> [rbp-0x10] do-not-enreg[XS] addr-exposed "impSpillStackEnsure"
  1500. ;
  1501. ; Lcl frame size = 48
  1502. Setting stack level from -572662307 to 0
  1503.  
  1504. =============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000004.40030060: i internal label target LIR
  1505. BB01 IN (0)={} + ByrefExposed + GcHeap
  1506. OUT(0)={} + ByrefExposed + GcHeap
  1507.  
  1508. Liveness not changing: 0000000000000000 {}
  1509. Live regs: (unchanged) 00000000 {}
  1510. GC regs: (unchanged) 00000000 {}
  1511. Byref regs: (unchanged) 00000000 {}
  1512.  
  1513. L_M17050_BB01:
  1514. Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  1515.  
  1516. =============== Generating BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.40000040: internal LIR
  1517. BB02 IN (0)={} + ByrefExposed + GcHeap
  1518. OUT(0)={} + ByrefExposed + GcHeap
  1519.  
  1520. Liveness not changing: 0000000000000000 {}
  1521. Live regs: (unchanged) 00000000 {}
  1522. GC regs: (unchanged) 00000000 {}
  1523. Byref regs: (unchanged) 00000000 {}
  1524.  
  1525. L_M17050_BB02:
  1526. Added IP mapping: NO_MAP STACK_EMPTY (G_M17050_IG02,ins#0,ofs#0) label
  1527. Generating: N004 ( 3, 10) [000010] -c---------- t10 = CNS_INT(h) long 0x7fff4561eaf0 token REG NA
  1528. /--* t10 long
  1529. Generating: N006 ( 5, 12) [000011] nc---------- t11 = * IND int REG NA
  1530. Generating: N008 ( 1, 1) [000012] -c---------- t12 = CNS_INT int 0 REG NA
  1531. /--* t11 int
  1532. +--* t12 int
  1533. Generating: N010 ( 7, 14) [000013] J------N---- * EQ void REG NA
  1534. IN0001: cmp dword ptr [(reloc 0x7fff4561eaf0)], 0
  1535. Generating: N012 ( 9, 16) [000018] ------------ * JTRUE void REG NA
  1536. IN0002: je L_M17050_BB04
  1537.  
  1538. =============== Generating BB03 [???..???), preds={BB02} succs={BB04} flags=0x00000000.40000040: internal LIR
  1539. BB03 IN (0)={} + ByrefExposed + GcHeap
  1540. OUT(0)={} + ByrefExposed + GcHeap
  1541.  
  1542. Liveness not changing: 0000000000000000 {}
  1543. Live regs: (unchanged) 00000000 {}
  1544. GC regs: (unchanged) 00000000 {}
  1545. Byref regs: (unchanged) 00000000 {}
  1546.  
  1547. L_M17050_BB03:
  1548.  
  1549. G_M17050_IG02: ; offs=000000H, funclet=00, bbWeight=1
  1550. Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  1551. genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
  1552. Generating: N016 ( 14, 5) [000014] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  1553. Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  1554. IN0003: call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  1555.  
  1556. =============== Generating BB04 [???..???), preds={BB02,BB03} succs={BB05} flags=0x00000000.40030060: i internal label target LIR
  1557. BB04 IN (0)={} + ByrefExposed + GcHeap
  1558. OUT(0)={} + ByrefExposed + GcHeap
  1559.  
  1560. Liveness not changing: 0000000000000000 {}
  1561. Live regs: (unchanged) 00000000 {}
  1562. GC regs: (unchanged) 00000000 {}
  1563. Byref regs: (unchanged) 00000000 {}
  1564.  
  1565. L_M17050_BB04:
  1566.  
  1567. G_M17050_IG03: ; offs=00000DH, funclet=00, bbWeight=0.50
  1568. Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  1569. genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
  1570.  
  1571. =============== Generating BB05 [000..008) (return), preds={BB04} succs={} flags=0x00000004.40080020: i gcsafe LIR
  1572. BB05 IN (0)={} + ByrefExposed + GcHeap
  1573. OUT(0)={} + ByrefExposed + GcHeap
  1574.  
  1575. Liveness not changing: 0000000000000000 {}
  1576. Live regs: (unchanged) 00000000 {}
  1577. GC regs: (unchanged) 00000000 {}
  1578. Byref regs: (unchanged) 00000000 {}
  1579.  
  1580. L_M17050_BB05:
  1581. Added IP mapping: 0x0000 STACK_EMPTY (G_M17050_IG04,ins#0,ofs#0) label
  1582. Generating: N022 (???,???) [000019] ------------ IL_OFFSET void IL offset: 0x0 REG NA
  1583. Generating: N024 ( 1, 1) [000000] ------------ NO_OP void REG NA
  1584. IN0004: nop
  1585. Added IP mapping: 0x0001 STACK_EMPTY (G_M17050_IG04,ins#1,ofs#1)
  1586. Generating: N026 (???,???) [000020] ------------ IL_OFFSET void IL offset: 0x1 REG NA
  1587. Generating: N028 ( 14, 5) [000001] --CXG------- t1 = CALL simd16 CoreLab.Program.Callee REG mm0
  1588. Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  1589. Added IP mapping: 0x0001 STACK_EMPTY CALL_INSTRUCTION (G_M17050_IG04,ins#1,ofs#1)
  1590. IN0005: call CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1591. IN0006: vmovaps xmm0, xrax
  1592. /--* t1 simd16
  1593. Generating: N030 ( 18, 8) [000004] DA-XG------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1 NA REG NA
  1594. IN0007: vmovapd xmmword ptr [V01 rbp-10H], xmm0
  1595. Added IP mapping: 0x0006 (G_M17050_IG04,ins#4,ofs#17)
  1596. Generating: N032 (???,???) [000021] ------------ IL_OFFSET void IL offset: 0x6 REG NA
  1597. Generating: N034 ( 0, 0) [000007] ------------ NOP void REG NA
  1598. IN0008: nop
  1599. Added IP mapping: 0x0007 STACK_EMPTY (G_M17050_IG04,ins#5,ofs#18)
  1600. Generating: N036 (???,???) [000022] ------------ IL_OFFSET void IL offset: 0x7 REG NA
  1601. Generating: N038 ( 0, 0) [000009] ------------ RETURN void REG NA
  1602. IN0009: nop
  1603. Added IP mapping: EPILOG STACK_EMPTY (G_M17050_IG04,ins#6,ofs#19) label
  1604. Reserving epilog IG for block BB05
  1605.  
  1606. G_M17050_IG04: ; offs=000012H, funclet=00, bbWeight=1
  1607. *************** After placeholder IG creation
  1608. G_M17050_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
  1609. G_M17050_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1610. G_M17050_IG03: ; offs=00000DH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1611. G_M17050_IG04: ; offs=000012H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1612. G_M17050_IG05: ; epilog placeholder, next placeholder=<END>, BB05 [0000], epilog, extend <-- First placeholder <-- Last placeholder
  1613. ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
  1614. ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
  1615. Liveness not changing: 0000000000000000 {}
  1616.  
  1617. # compCycleEstimate = 42, compSizeEstimate = 30 CoreLab.Program:Caller()
  1618. ; Final local variable assignments
  1619. ;
  1620. ; V00 OutArgs [V00 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
  1621. ; V01 tmp1 [V01 ] ( 1, 1 ) simd16 -> [rbp-0x10] do-not-enreg[XS] addr-exposed "impSpillStackEnsure"
  1622. ;
  1623. ; Lcl frame size = 48
  1624. *************** Before prolog / epilog generation
  1625. G_M17050_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
  1626. G_M17050_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1627. G_M17050_IG03: ; offs=00000DH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1628. G_M17050_IG04: ; offs=000012H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1629. G_M17050_IG05: ; epilog placeholder, next placeholder=<END>, BB05 [0000], epilog, extend <-- First placeholder <-- Last placeholder
  1630. ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
  1631. ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
  1632. *************** In genFnProlog()
  1633. Added IP mapping to front: PROLOG STACK_EMPTY (G_M17050_IG01,ins#0,ofs#0) label
  1634.  
  1635. __prolog:
  1636. IN000a: push rbp
  1637. IN000b: sub rsp, 48
  1638. IN000c: lea rbp, [rsp+30H]
  1639. *************** In genEnregisterIncomingStackArgs()
  1640.  
  1641.  
  1642. G_M17050_IG01: ; offs=000000H, funclet=00, bbWeight=1
  1643. *************** In genFnEpilog()
  1644.  
  1645. __epilog:
  1646. gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
  1647. IN000d: lea rsp, [rbp]
  1648. IN000e: pop rbp
  1649. IN000f: ret
  1650.  
  1651. G_M17050_IG05: ; offs=000025H, funclet=00, bbWeight=1
  1652. 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
  1653. *************** After prolog / epilog generation
  1654. G_M17050_IG01: ; func=00, offs=000000H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  1655. G_M17050_IG02: ; offs=00000AH, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1656. G_M17050_IG03: ; offs=000017H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1657. G_M17050_IG04: ; offs=00001CH, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1658. G_M17050_IG05: ; offs=00002FH, size=0006H, epilog, nogc, extend
  1659. *************** In emitJumpDistBind()
  1660. Binding: IN0002: 000000 je L_M17050_BB04
  1661. Binding L_M17050_BB04to G_M17050_IG04
  1662. Estimate of fwd jump [647DCC64/002]: 0011 -> 001C = 0009
  1663. Shrinking jump [647DCC64/002]
  1664. Adjusted offset of BB03 from 0017 to 0013
  1665. Adjusted offset of BB04 from 001C to 0018
  1666. Adjusted offset of BB05 from 002F to 002B
  1667. Total shrinkage = 4, min extra jump size = 4294967295
  1668.  
  1669. Hot code size = 0x31 bytes
  1670. Cold code size = 0x0 bytes
  1671. reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x8)
  1672. *************** In emitEndCodeGen()
  1673. Converting emitMaxStackDepth from bytes (0) to elements (0)
  1674.  
  1675. ***************************************************************************
  1676. Instructions as they come out of the scheduler
  1677.  
  1678.  
  1679. G_M17050_IG01: ; func=00, offs=000000H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  1680. IN000a: 000000 55 push rbp
  1681. IN000b: 000001 4883EC30 sub rsp, 48
  1682. IN000c: 000005 488D6C2430 lea rbp, [rsp+30H]
  1683. ;; bbWeight=1 PerfScore 1.75
  1684. G_M17050_IG02: ; func=00, offs=00000AH, size=0009H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  1685. IN0001: 00000A 833DDF6D1F0000 cmp dword ptr [(reloc 0x7fff4561eaf0)], 0
  1686. IN0002: 000011 7405 je SHORT G_M17050_IG04
  1687. ;; bbWeight=1 PerfScore 3.00
  1688. G_M17050_IG03: ; func=00, offs=000013H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1689. [647DD398] ptr arg pop 0
  1690. IN0003: 000013 E828B3A15E call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  1691. ;; bbWeight=0.50 PerfScore 0.50
  1692. G_M17050_IG04: ; func=00, offs=000018H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1693. IN0004: 000018 90 nop
  1694. [647DD3B8] ptr arg pop 0
  1695. IN0005: 000019 E8BA94FFFF call CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1696. IN0006: 00001E C5F828C0 vmovaps xmm0, xrax (ECS:5, ACS:4)
  1697. Instruction predicted size = 5, actual = 4
  1698. IN0007: 000022 C5F92945F0 vmovapd xmmword ptr [rbp-10H], xmm0 (ECS:6, ACS:5)
  1699. Instruction predicted size = 6, actual = 5
  1700. IN0008: 000027 90 nop
  1701. IN0009: 000028 90 nop
  1702. ;; bbWeight=1 PerfScore 4.00
  1703. G_M17050_IG05: ; func=00, offs=00002BH, size=0006H, epilog, nogc, extend
  1704. Block predicted offs = 0000002B, actual = 00000029 -> size adj = 2
  1705. IN000d: 000029 488D6500 lea rsp, [rbp]
  1706. IN000e: 00002D 5D pop rbp
  1707. IN000f: 00002E C3 ret
  1708. ;; bbWeight=1 PerfScore 2.00Allocated method code size = 49 , actual size = 47
  1709.  
  1710. ; Total bytes of code 47, prolog size 10, PerfScore 16.15, (MethodHash=4dbcbd65) for method CoreLab.Program:Caller()
  1711. ; ============================================================
  1712.  
  1713. *************** After end code gen, before unwindEmit()
  1714. G_M17050_IG01: ; func=00, offs=000000H, size=000AH, bbWeight=1 PerfScore 1.75, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  1715.  
  1716. IN000a: 000000 push rbp
  1717. IN000b: 000001 sub rsp, 48
  1718. IN000c: 000005 lea rbp, [rsp+30H]
  1719.  
  1720. G_M17050_IG02: ; offs=00000AH, size=0009H, bbWeight=1 PerfScore 3.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  1721.  
  1722. IN0001: 00000A cmp dword ptr [(reloc 0x7fff4561eaf0)], 0
  1723. IN0002: 000011 je SHORT G_M17050_IG04
  1724.  
  1725. G_M17050_IG03: ; offs=000013H, size=0005H, bbWeight=0.50 PerfScore 0.50, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1726.  
  1727. IN0003: 000013 call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  1728.  
  1729. G_M17050_IG04: ; offs=000018H, size=0011H, bbWeight=1 PerfScore 4.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  1730.  
  1731. IN0004: 000018 nop
  1732. IN0005: 000019 call CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1733. IN0006: 00001E vmovaps xmm0, xrax
  1734. IN0007: 000022 vmovapd xmmword ptr [V01 rbp-10H], xmm0
  1735. IN0008: 000027 nop
  1736. IN0009: 000028 nop
  1737.  
  1738. G_M17050_IG05: ; offs=000029H, size=0006H, bbWeight=1 PerfScore 2.00, epilog, nogc, extend
  1739.  
  1740. IN000d: 000029 lea rsp, [rbp]
  1741. IN000e: 00002D pop rbp
  1742. IN000f: 00002E ret
  1743.  
  1744. Unwind Info:
  1745. >> Start offset : 0x000000 (not in unwind data)
  1746. >> End offset : 0x00002f (not in unwind data)
  1747. Version : 1
  1748. Flags : 0x00
  1749. SizeOfProlog : 0x05
  1750. CountOfUnwindCodes: 2
  1751. FrameRegister : none (0)
  1752. FrameOffset : N/A (no FrameRegister) (Value=0)
  1753. UnwindCodes :
  1754. CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 5 * 8 + 8 = 48 = 0x30
  1755. CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
  1756. allocUnwindInfo(pHotCode=0x00007FFF45427D00, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x2f, unwindSize=0x8, pUnwindBlock=0x000001A2647DA698, funKind=0 (main function))
  1757. *************** In genIPmappingGen()
  1758. IP mapping count : 8
  1759. IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
  1760. IL offs NO_MAP : 0x0000000A ( STACK_EMPTY )
  1761. IL offs 0x0000 : 0x00000018 ( STACK_EMPTY )
  1762. IL offs 0x0001 : 0x00000019 ( STACK_EMPTY )
  1763. IL offs 0x0001 : 0x00000019 ( STACK_EMPTY CALL_INSTRUCTION )
  1764. IL offs 0x0006 : 0x00000027
  1765. IL offs 0x0007 : 0x00000028 ( STACK_EMPTY )
  1766. IL offs EPILOG : 0x00000029 ( STACK_EMPTY )
  1767.  
  1768. *************** In genSetScopeInfo()
  1769. VarLocInfo count is 0
  1770. *************** Variable debug info
  1771. 0 live ranges
  1772. *************** In gcInfoBlockHdrSave()
  1773. Set code length to 47.
  1774. Set ReturnKind to Scalar.
  1775. Set stack base register to rbp.
  1776. Set Outgoing stack arg area size to 32.
  1777. Defining interruptible range: [0xa, 0x29).
  1778. Method code size: 47
  1779.  
  1780. Allocations for CoreLab.Program:Caller() (MethodHash=4dbcbd65)
  1781. count: 240, size: 25060, max = 2640
  1782. allocateMemory: 65536, nraUsed: 27472
  1783.  
  1784. Alloc'd bytes by kind:
  1785. kind | size | pct
  1786. ---------------------+------------+--------
  1787. AssertionProp | 0 | 0.00%
  1788. ASTNode | 3184 | 12.71%
  1789. InstDesc | 2944 | 11.75%
  1790. ImpStack | 384 | 1.53%
  1791. BasicBlock | 1936 | 7.73%
  1792. fgArgInfo | 0 | 0.00%
  1793. fgArgInfoPtrArr | 0 | 0.00%
  1794. FlowList | 160 | 0.64%
  1795. TreeStatementList | 0 | 0.00%
  1796. SiScope | 0 | 0.00%
  1797. DominatorMemory | 0 | 0.00%
  1798. LSRA | 3208 | 12.80%
  1799. LSRA_Interval | 88 | 0.35%
  1800. LSRA_RefPosition | 2176 | 8.68%
  1801. Reachability | 0 | 0.00%
  1802. SSA | 0 | 0.00%
  1803. ValueNumber | 0 | 0.00%
  1804. LvaTable | 1920 | 7.66%
  1805. UnwindInfo | 0 | 0.00%
  1806. hashBv | 80 | 0.32%
  1807. bitset | 56 | 0.22%
  1808. FixedBitVect | 8 | 0.03%
  1809. Generic | 1230 | 4.91%
  1810. LocalAddressVisitor | 0 | 0.00%
  1811. FieldSeqStore | 0 | 0.00%
  1812. ZeroOffsetFieldMap | 40 | 0.16%
  1813. ArrayInfoMap | 0 | 0.00%
  1814. MemoryPhiArg | 0 | 0.00%
  1815. CSE | 0 | 0.00%
  1816. GC | 1392 | 5.55%
  1817. CorSig | 104 | 0.42%
  1818. Inlining | 120 | 0.48%
  1819. ArrayStack | 0 | 0.00%
  1820. DebugInfo | 256 | 1.02%
  1821. DebugOnly | 4414 | 17.61%
  1822. Codegen | 1128 | 4.50%
  1823. LoopOpt | 0 | 0.00%
  1824. LoopHoist | 0 | 0.00%
  1825. Unknown | 160 | 0.64%
  1826. RangeCheck | 0 | 0.00%
  1827. CopyProp | 0 | 0.00%
  1828. SideEffects | 0 | 0.00%
  1829. ObjectAllocator | 0 | 0.00%
  1830. VariableLiveRanges | 0 | 0.00%
  1831. ClassLayout | 72 | 0.29%
  1832. TailMergeThrows | 0 | 0.00%
  1833.  
  1834. ****** DONE compiling CoreLab.Program:Caller()
  1835. ****** START compiling CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double] (MethodHash=f5b01313)
  1836. Generating code for Windows x64
  1837. OPTIONS: compCodeOpt = BLENDED_CODE
  1838. OPTIONS: compDbgCode = true
  1839. OPTIONS: compDbgInfo = true
  1840. OPTIONS: compDbgEnC = false
  1841. OPTIONS: compProcedureSplitting = false
  1842. OPTIONS: compProcedureSplittingEH = false
  1843. IL to import:
  1844. IL_0000 00 nop
  1845. IL_0001 12 00 ldloca.s 0x0
  1846. IL_0003 fe 15 01 00 00 1b initobj 0x1B000001
  1847. IL_0009 06 ldloc.0
  1848. IL_000a 0b stloc.1
  1849. IL_000b 2b 00 br.s 0 (IL_000d)
  1850. IL_000d 07 ldloc.1
  1851. IL_000e 2a ret
  1852. HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Double
  1853. Found type Hardware Intrinsic SIMD Vector128<double>
  1854. Known type Vector128<double>
  1855. Known type Vector128<double>
  1856. Known type Vector128<double>
  1857. Known type Vector128<double>
  1858. Known type Vector128<double>
  1859.  
  1860. lvaGrabTemp returning 2 (V02 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
  1861. ; Initial local variable assignments
  1862. ;
  1863. ; V00 loc0 simd16
  1864. ; V01 loc1 simd16
  1865. ; V02 OutArgs lclBlk (na) "OutgoingArgSpace"
  1866. *************** In compInitDebuggingInfo() for CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1867. getVars() returned cVars = 0, extendOthers = true
  1868. info.compVarScopesCount = 2
  1869. VarNum LVNum Name Beg End
  1870. 0: 00h 00h V00 loc0 000h 00Fh
  1871. 1: 01h 01h V01 loc1 000h 00Fh
  1872. New Basic Block BB01 [0000] created.
  1873. New scratch BB01
  1874. Debuggable code - Add new BB01 [0000] to perform initialization of variables
  1875. info.compStmtOffsetsCount = 0
  1876. info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE )
  1877. *************** In fgFindBasicBlocks() for CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1878. Marked V01 as a single def local
  1879. Jump targets:
  1880. IL_000d
  1881. New Basic Block BB02 [0001] created.
  1882. BB02 [000..00D)
  1883. New Basic Block BB03 [0002] created.
  1884. BB03 [00D..00F)
  1885. CLFLG_MINOPT set for method CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1886. IL Code Size,Instr 15, 8, Basic Block count 3, Local Variable Num,Ref count 3, 4 for method CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1887. IL Code Size,Instr 15, 8, Basic Block count 3, Local Variable Num,Ref count 3, 4 for method CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1888. OPTIONS: opts.MinOpts() == true
  1889. Basic block list for 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  1890.  
  1891. -----------------------------------------------------------------------------------------------------------------------------------------
  1892. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  1893. -----------------------------------------------------------------------------------------------------------------------------------------
  1894. BB01 [0000] 1 1 [???..???) i internal
  1895. BB02 [0001] 1 1 [000..00D)-> BB03 (always)
  1896. BB03 [0002] 1 1 [00D..00F) (return)
  1897. -----------------------------------------------------------------------------------------------------------------------------------------
  1898. *************** In impImport() for CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1899. Marking leading BBF_INTERNAL block BB01 as BBF_IMPORTED
  1900.  
  1901. impImportBlockPending for BB02
  1902.  
  1903. Importing BB02 (PC=000) of 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  1904. [ 0] 0 (0x000) nop
  1905.  
  1906. STMT00001 (IL 0x000... ???)
  1907. [000001] ------------ * NO_OP void
  1908.  
  1909. [ 0] 1 (0x001) ldloca.s 0
  1910. [ 1] 3 (0x003) initobj 1B000001
  1911.  
  1912. STMT00002 (IL 0x001... ???)
  1913. [000005] IA---------- * ASG simd16 (init)
  1914. [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  1915. [000004] ------------ \--* CNS_INT int 0
  1916.  
  1917. [ 0] 9 (0x009) ldloc.0
  1918. [ 1] 10 (0x00a) stloc.1
  1919.  
  1920. STMT00003 (IL 0x009... ???)
  1921. [000009] -A---------- * ASG simd16 (copy)
  1922. [000007] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  1923. [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  1924.  
  1925. [ 0] 11 (0x00b) br.s
  1926.  
  1927. STMT00004 (IL 0x00B... ???)
  1928. [000010] ------------ * NOP void
  1929.  
  1930. impImportBlockPending for BB03
  1931.  
  1932. Importing BB03 (PC=013) of 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  1933. [ 0] 13 (0x00d) ldloc.1
  1934. [ 1] 14 (0x00e) ret
  1935. impFixupStructReturnType: retyping
  1936. [000011] ------------ * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  1937.  
  1938. impFixupStructReturnType: result of retyping is
  1939. [000011] ------------ * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  1940.  
  1941.  
  1942. STMT00005 (IL 0x00D... ???)
  1943. [000012] ------------ * RETURN simd16
  1944. [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  1945.  
  1946. *************** in fgTransformIndirectCalls(root)
  1947. -- no candidates to transform
  1948.  
  1949. New BlockSet epoch 1, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
  1950. *************** In fgMorph()
  1951. *************** In fgDebugCheckBBlist
  1952. *************** In Allocate Objects
  1953. Trees before Allocate Objects
  1954.  
  1955. -----------------------------------------------------------------------------------------------------------------------------------------
  1956. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  1957. -----------------------------------------------------------------------------------------------------------------------------------------
  1958. BB01 [0000] 1 1 [???..???) i internal
  1959. BB02 [0001] 1 1 [000..00D)-> BB03 (always) i
  1960. BB03 [0002] 1 1 [00D..00F) (return) i
  1961. -----------------------------------------------------------------------------------------------------------------------------------------
  1962.  
  1963. ------------ BB01 [???..???), preds={} succs={BB02}
  1964.  
  1965. ***** BB01
  1966. STMT00000 (IL ???... ???)
  1967. [000000] ------------ * NOP void
  1968.  
  1969. ------------ BB02 [000..00D) -> BB03 (always), preds={} succs={BB03}
  1970.  
  1971. ***** BB02
  1972. STMT00001 (IL 0x000...0x000)
  1973. [000001] ------------ * NO_OP void
  1974.  
  1975. ***** BB02
  1976. STMT00002 (IL 0x001...0x004)
  1977. [000005] IA---------- * ASG simd16 (init)
  1978. [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  1979. [000004] ------------ \--* CNS_INT int 0
  1980.  
  1981. ***** BB02
  1982. STMT00003 (IL 0x009...0x00A)
  1983. [000009] -A---------- * ASG simd16 (copy)
  1984. [000007] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  1985. [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  1986.  
  1987. ***** BB02
  1988. STMT00004 (IL 0x00B...0x00B)
  1989. [000010] ------------ * NOP void
  1990.  
  1991. ------------ BB03 [00D..00F) (return), preds={} succs={}
  1992.  
  1993. ***** BB03
  1994. STMT00005 (IL 0x00D...0x00E)
  1995. [000012] ------------ * RETURN simd16
  1996. [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  1997.  
  1998. -------------------------------------------------------------------------------------------------------------------
  1999.  
  2000. *** ObjectAllocationPhase: no newobjs in this method; punting
  2001. *************** Exiting Allocate Objects
  2002. Trees after Allocate Objects
  2003.  
  2004. -----------------------------------------------------------------------------------------------------------------------------------------
  2005. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2006. -----------------------------------------------------------------------------------------------------------------------------------------
  2007. BB01 [0000] 1 1 [???..???) i internal
  2008. BB02 [0001] 1 1 [000..00D)-> BB03 (always) i
  2009. BB03 [0002] 1 1 [00D..00F) (return) i
  2010. -----------------------------------------------------------------------------------------------------------------------------------------
  2011.  
  2012. ------------ BB01 [???..???), preds={} succs={BB02}
  2013.  
  2014. ***** BB01
  2015. STMT00000 (IL ???... ???)
  2016. [000000] ------------ * NOP void
  2017.  
  2018. ------------ BB02 [000..00D) -> BB03 (always), preds={} succs={BB03}
  2019.  
  2020. ***** BB02
  2021. STMT00001 (IL 0x000...0x000)
  2022. [000001] ------------ * NO_OP void
  2023.  
  2024. ***** BB02
  2025. STMT00002 (IL 0x001...0x004)
  2026. [000005] IA---------- * ASG simd16 (init)
  2027. [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2028. [000004] ------------ \--* CNS_INT int 0
  2029.  
  2030. ***** BB02
  2031. STMT00003 (IL 0x009...0x00A)
  2032. [000009] -A---------- * ASG simd16 (copy)
  2033. [000007] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2034. [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2035.  
  2036. ***** BB02
  2037. STMT00004 (IL 0x00B...0x00B)
  2038. [000010] ------------ * NOP void
  2039.  
  2040. ------------ BB03 [00D..00F) (return), preds={} succs={}
  2041.  
  2042. ***** BB03
  2043. STMT00005 (IL 0x00D...0x00E)
  2044. [000012] ------------ * RETURN simd16
  2045. [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2046.  
  2047. -------------------------------------------------------------------------------------------------------------------
  2048.  
  2049. *************** After fgAddInternal()
  2050.  
  2051. -----------------------------------------------------------------------------------------------------------------------------------------
  2052. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2053. -----------------------------------------------------------------------------------------------------------------------------------------
  2054. BB01 [0000] 1 1 [???..???) i internal
  2055. BB02 [0001] 1 1 [000..00D)-> BB03 (always) i
  2056. BB03 [0002] 1 1 [00D..00F) (return) i
  2057. -----------------------------------------------------------------------------------------------------------------------------------------
  2058.  
  2059. *************** Exception Handling table is empty
  2060. *************** In fgDebugCheckBBlist
  2061.  
  2062. *************** In fgRemoveEmptyTry()
  2063. No EH in this method, nothing to remove.
  2064.  
  2065. *************** In fgRemoveEmptyFinally()
  2066. No EH in this method, nothing to remove.
  2067.  
  2068. *************** In fgMergeFinallyChains()
  2069. No EH in this method, nothing to merge.
  2070.  
  2071. *************** In fgCloneFinally()
  2072. No EH in this method, no cloning.
  2073.  
  2074. *************** In fgResetImplicitByRefRefCount()
  2075. *************** In fgPromoteStructs()
  2076. promotion opt flag not enabled
  2077.  
  2078. *************** In fgMarkAddressExposedLocals()
  2079. LocalAddressVisitor visiting statement:
  2080. STMT00000 (IL ???... ???)
  2081. [000000] ------------ * NOP void
  2082.  
  2083. LocalAddressVisitor visiting statement:
  2084. STMT00006 (IL ???... ???)
  2085. [000020] --C-G------- * QMARK void
  2086. [000016] Q----------- if +--* EQ int
  2087. [000014] ------------ | +--* IND int
  2088. [000013] ------------ | | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  2089. [000015] ------------ | \--* CNS_INT int 0
  2090. [000019] --C-G------- if \--* COLON void
  2091. [000017] --C-G------- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2092. [000018] ------------ then \--* NOP void
  2093.  
  2094. LocalAddressVisitor visiting statement:
  2095. STMT00001 (IL 0x000...0x000)
  2096. [000001] ------------ * NO_OP void
  2097.  
  2098. LocalAddressVisitor visiting statement:
  2099. STMT00002 (IL 0x001...0x004)
  2100. [000005] IA---------- * ASG simd16 (init)
  2101. [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2102. [000004] ------------ \--* CNS_INT int 0
  2103.  
  2104. LocalAddressVisitor visiting statement:
  2105. STMT00003 (IL 0x009...0x00A)
  2106. [000009] -A---------- * ASG simd16 (copy)
  2107. [000007] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2108. [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2109.  
  2110. LocalAddressVisitor visiting statement:
  2111. STMT00004 (IL 0x00B...0x00B)
  2112. [000010] ------------ * NOP void
  2113.  
  2114. LocalAddressVisitor visiting statement:
  2115. STMT00005 (IL 0x00D...0x00E)
  2116. [000012] ------------ * RETURN simd16
  2117. [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2118.  
  2119.  
  2120. *************** In fgRetypeImplicitByRefArgs()
  2121.  
  2122. *************** In fgMorphBlocks()
  2123.  
  2124. Morphing BB01 of 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  2125.  
  2126. fgMorphTree BB01, STMT00000 (before)
  2127. [000000] ------------ * NOP void
  2128.  
  2129. fgMorphTree BB01, STMT00006 (before)
  2130. [000020] --C-G------- * QMARK void
  2131. [000016] Q----------- if +--* EQ int
  2132. [000014] ------------ | +--* IND int
  2133. [000013] ------------ | | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  2134. [000015] ------------ | \--* CNS_INT int 0
  2135. [000019] --C-G------- if \--* COLON void
  2136. [000017] --C-G------- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2137. [000018] ------------ then \--* NOP void
  2138. Initializing arg info for 17.CALL:
  2139. ArgTable for 17.CALL after fgInitArgInfo:
  2140.  
  2141. Morphing args for 17.CALL:
  2142. argSlots=0, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
  2143. ArgTable for 17.CALL after fgMorphArgs:
  2144.  
  2145.  
  2146. Morphing BB02 of 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  2147.  
  2148. fgMorphTree BB02, STMT00001 (before)
  2149. [000001] ------------ * NO_OP void
  2150.  
  2151. fgMorphTree BB02, STMT00002 (before)
  2152. [000005] IA---------- * ASG simd16 (init)
  2153. [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2154. [000004] ------------ \--* CNS_INT int 0
  2155.  
  2156. fgMorphInitBlock:fgMorphOneAsgBlock (after):
  2157. [000005] -A---------- * ASG simd16 (copy)
  2158. [000002] D----+-N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2159. [000021] ------------ \--* SIMD simd16 double init
  2160. [000004] -----+------ \--* CNS_INT int 0
  2161. using oneAsgTree.
  2162.  
  2163. fgMorphTree BB02, STMT00002 (after)
  2164. [000005] -A---+------ * ASG simd16 (copy)
  2165. [000002] D----+-N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2166. [000021] ------------ \--* SIMD simd16 double init
  2167. [000004] -----+------ \--* CNS_INT int 0
  2168.  
  2169. fgMorphTree BB02, STMT00003 (before)
  2170. [000009] -A---------- * ASG simd16 (copy)
  2171. [000007] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2172. [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2173.  
  2174. fgMorphCopyBlock:fgMorphOneAsgBlock (after):
  2175. [000009] -A---------- * ASG simd16 (copy)
  2176. [000007] D----+-N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2177. [000006] -----+------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2178. using oneAsgTree.
  2179.  
  2180. fgMorphCopyBlock (after):
  2181. [000009] -A---------- * ASG simd16 (copy)
  2182. [000007] D----+-N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2183. [000006] -----+------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2184.  
  2185. fgMorphTree BB02, STMT00004 (before)
  2186. [000010] ------------ * NOP void
  2187.  
  2188. Morphing BB03 of 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  2189.  
  2190. fgMorphTree BB03, STMT00005 (before)
  2191. [000012] ------------ * RETURN simd16
  2192. [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2193.  
  2194. Expanding top-level qmark in BB01 (before)
  2195.  
  2196. -----------------------------------------------------------------------------------------------------------------------------------------
  2197. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2198. -----------------------------------------------------------------------------------------------------------------------------------------
  2199. BB01 [0000] 1 1 [???..???) i internal
  2200. -----------------------------------------------------------------------------------------------------------------------------------------
  2201.  
  2202. ------------ BB01 [???..???), preds={} succs={BB02}
  2203.  
  2204. ***** BB01
  2205. STMT00000 (IL ???... ???)
  2206. [000000] -----+------ * NOP void
  2207.  
  2208. ***** BB01
  2209. STMT00006 (IL ???... ???)
  2210. [000020] --C-G+------ * QMARK void
  2211. [000016] J----+-N---- if +--* EQ int
  2212. [000014] n----+------ | +--* IND int
  2213. [000013] -----+------ | | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  2214. [000015] -----+------ | \--* CNS_INT int 0
  2215. [000019] --C-G+?----- if \--* COLON void
  2216. [000017] --C-G+?----- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2217. [000018] -----+?----- then \--* NOP void
  2218.  
  2219. -------------------------------------------------------------------------------------------------------------------
  2220. New Basic Block BB04 [0003] created.
  2221. BB02 previous predecessor was BB01, now is BB04
  2222. New Basic Block BB05 [0004] created.
  2223. New Basic Block BB06 [0005] created.
  2224.  
  2225. Removing statement STMT00006 (IL ???... ???)
  2226. [000020] --C-G+------ * QMARK void
  2227. [000016] J----+-N---- if +--* EQ int
  2228. [000014] n----+------ | +--* IND int
  2229. [000013] -----+------ | | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  2230. [000015] -----+------ | \--* CNS_INT int 0
  2231. [000019] --C-G+?----- if \--* COLON void
  2232. [000017] --C-G+?----- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2233. [000018] -----+?----- then \--* NOP void
  2234. in BB01 as useless:
  2235.  
  2236.  
  2237. Expanding top-level qmark in BB01 (after)
  2238.  
  2239. -----------------------------------------------------------------------------------------------------------------------------------------
  2240. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2241. -----------------------------------------------------------------------------------------------------------------------------------------
  2242. BB01 [0000] 1 1 [???..???) i internal
  2243. BB05 [0004] 1 1 [???..???)-> BB04 ( cond ) internal
  2244. BB06 [0005] 1 0.50 [???..???) internal
  2245. BB04 [0003] 2 1 [???..???) i internal label target
  2246. -----------------------------------------------------------------------------------------------------------------------------------------
  2247.  
  2248. ------------ BB01 [???..???), preds={} succs={BB05}
  2249.  
  2250. ***** BB01
  2251. STMT00000 (IL ???... ???)
  2252. [000000] -----+------ * NOP void
  2253.  
  2254. ------------ BB05 [???..???) -> BB04 (cond), preds={} succs={BB06,BB04}
  2255.  
  2256. ***** BB05
  2257. STMT00007 (IL ???... ???)
  2258. [000022] ------------ * JTRUE void
  2259. [000016] J----+-N---- \--* EQ int
  2260. [000014] n----+------ +--* IND int
  2261. [000013] -----+------ | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  2262. [000015] -----+------ \--* CNS_INT int 0
  2263.  
  2264. ------------ BB06 [???..???), preds={} succs={BB04}
  2265.  
  2266. ***** BB06
  2267. STMT00008 (IL ???... ???)
  2268. [000017] --C-G+?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2269.  
  2270. ------------ BB04 [???..???), preds={} succs={BB02}
  2271.  
  2272. -------------------------------------------------------------------------------------------------------------------
  2273.  
  2274. Renumbering the basic blocks for fgComputePred
  2275.  
  2276. *************** Before renumbering the basic blocks
  2277.  
  2278. -----------------------------------------------------------------------------------------------------------------------------------------
  2279. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2280. -----------------------------------------------------------------------------------------------------------------------------------------
  2281. BB01 [0000] 1 1 [???..???) i internal
  2282. BB05 [0004] 1 1 [???..???)-> BB04 ( cond ) internal
  2283. BB06 [0005] 1 0.50 [???..???) internal
  2284. BB04 [0003] 2 1 [???..???) i internal label target
  2285. BB02 [0001] 1 1 [000..00D)-> BB03 (always) i
  2286. BB03 [0002] 1 1 [00D..00F) (return) i
  2287. -----------------------------------------------------------------------------------------------------------------------------------------
  2288.  
  2289. *************** Exception Handling table is empty
  2290. Renumber BB05 to BB02
  2291. Renumber BB06 to BB03
  2292. Renumber BB02 to BB05
  2293. Renumber BB03 to BB06
  2294.  
  2295. *************** After renumbering the basic blocks
  2296.  
  2297. -----------------------------------------------------------------------------------------------------------------------------------------
  2298. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2299. -----------------------------------------------------------------------------------------------------------------------------------------
  2300. BB01 [0000] 1 1 [???..???) i internal
  2301. BB02 [0004] 1 1 [???..???)-> BB04 ( cond ) internal
  2302. BB03 [0005] 1 0.50 [???..???) internal
  2303. BB04 [0003] 2 1 [???..???) i internal label target
  2304. BB05 [0001] 1 1 [000..00D)-> BB06 (always) i
  2305. BB06 [0002] 1 1 [00D..00F) (return) i
  2306. -----------------------------------------------------------------------------------------------------------------------------------------
  2307.  
  2308. *************** Exception Handling table is empty
  2309.  
  2310. New BlockSet epoch 2, # of blocks (including unused BB00): 7, bitset array size: 1 (short)
  2311.  
  2312. *************** In fgComputePreds()
  2313.  
  2314. -----------------------------------------------------------------------------------------------------------------------------------------
  2315. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2316. -----------------------------------------------------------------------------------------------------------------------------------------
  2317. BB01 [0000] 1 1 [???..???) i internal
  2318. BB02 [0004] 1 1 [???..???)-> BB04 ( cond ) internal
  2319. BB03 [0005] 1 0.50 [???..???) internal
  2320. BB04 [0003] 2 1 [???..???) i internal label target
  2321. BB05 [0001] 1 1 [000..00D)-> BB06 (always) i
  2322. BB06 [0002] 1 1 [00D..00F) (return) i
  2323. -----------------------------------------------------------------------------------------------------------------------------------------
  2324.  
  2325.  
  2326. *************** After fgComputePreds()
  2327.  
  2328. -----------------------------------------------------------------------------------------------------------------------------------------
  2329. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2330. -----------------------------------------------------------------------------------------------------------------------------------------
  2331. BB01 [0000] 1 1 [???..???) i internal label target
  2332. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  2333. BB03 [0005] 1 BB02 0.50 [???..???) internal
  2334. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target
  2335. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i
  2336. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target
  2337. -----------------------------------------------------------------------------------------------------------------------------------------
  2338.  
  2339. *************** In fgComputeBlockAndEdgeWeights()
  2340.  
  2341. -----------------------------------------------------------------------------------------------------------------------------------------
  2342. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2343. -----------------------------------------------------------------------------------------------------------------------------------------
  2344. BB01 [0000] 1 1 [???..???) i internal label target
  2345. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  2346. BB03 [0005] 1 BB02 0.50 [???..???) internal
  2347. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target
  2348. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i
  2349. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target
  2350. -----------------------------------------------------------------------------------------------------------------------------------------
  2351.  
  2352. -- no profile data, so using default called count
  2353. -- not optimizing, so not computing edge weights
  2354. *************** In fgCreateFunclets()
  2355.  
  2356. After fgCreateFunclets()
  2357. -----------------------------------------------------------------------------------------------------------------------------------------
  2358. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2359. -----------------------------------------------------------------------------------------------------------------------------------------
  2360. BB01 [0000] 1 1 [???..???) i internal label target
  2361. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  2362. BB03 [0005] 1 BB02 0.50 [???..???) internal
  2363. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target
  2364. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i
  2365. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target
  2366. -----------------------------------------------------------------------------------------------------------------------------------------
  2367.  
  2368. *************** Exception Handling table is empty
  2369. *************** In fgDebugCheckBBlist
  2370.  
  2371. *************** In lvaMarkLocalVars()
  2372. *** lvaComputeRefCounts ***
  2373. *************** In fgFindOperOrder()
  2374. *************** In fgSetBlockOrder()
  2375. The biggest BB has 5 tree nodes
  2376.  
  2377. -----------------------------------------------------------------------------------------------------------------------------------------
  2378. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2379. -----------------------------------------------------------------------------------------------------------------------------------------
  2380. BB01 [0000] 1 1 [???..???) i internal label target
  2381. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  2382. BB03 [0005] 1 BB02 0.50 [???..???) internal
  2383. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target
  2384. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i
  2385. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target
  2386. -----------------------------------------------------------------------------------------------------------------------------------------
  2387.  
  2388. ------------ BB01 [???..???), preds={} succs={BB02}
  2389.  
  2390. ***** BB01
  2391. STMT00000 (IL ???... ???)
  2392. N001 ( 0, 0) [000000] ------------ * NOP void
  2393.  
  2394. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2395.  
  2396. ***** BB02
  2397. STMT00007 (IL ???... ???)
  2398. N005 ( 9, 16) [000022] ------------ * JTRUE void
  2399. N004 ( 7, 14) [000016] J------N---- \--* EQ int
  2400. N002 ( 5, 12) [000014] n----------- +--* IND int
  2401. N001 ( 3, 10) [000013] ------------ | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  2402. N003 ( 1, 1) [000015] ------------ \--* CNS_INT int 0
  2403.  
  2404. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2405.  
  2406. ***** BB03
  2407. STMT00008 (IL ???... ???)
  2408. N001 ( 14, 5) [000017] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2409.  
  2410. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2411.  
  2412. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2413.  
  2414. ***** BB05
  2415. STMT00001 (IL 0x000...0x000)
  2416. N001 ( 1, 1) [000001] ------------ * NO_OP void
  2417.  
  2418. ***** BB05
  2419. STMT00002 (IL 0x001...0x004)
  2420. N004 ( 6, 5) [000005] -A------R--- * ASG simd16 (copy)
  2421. N003 ( 3, 2) [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2422. N002 ( 2, 2) [000021] ------------ \--* SIMD simd16 double init
  2423. N001 ( 1, 1) [000004] ------------ \--* CNS_INT int 0
  2424.  
  2425. ***** BB05
  2426. STMT00003 (IL 0x009...0x00A)
  2427. N003 ( 7, 5) [000009] -A------R--- * ASG simd16 (copy)
  2428. N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2429. N001 ( 3, 2) [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2430.  
  2431. ***** BB05
  2432. STMT00004 (IL 0x00B...0x00B)
  2433. N001 ( 0, 0) [000010] ------------ * NOP void
  2434.  
  2435. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2436.  
  2437. ***** BB06
  2438. STMT00005 (IL 0x00D...0x00E)
  2439. N002 ( 4, 3) [000012] ------------ * RETURN simd16
  2440. N001 ( 3, 2) [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2441.  
  2442. -------------------------------------------------------------------------------------------------------------------
  2443.  
  2444.  
  2445. *************** In fgDetermineFirstColdBlock()
  2446. No procedure splitting will be done for this method
  2447. *************** In IR Rationalize
  2448. Trees before IR Rationalize
  2449.  
  2450. -----------------------------------------------------------------------------------------------------------------------------------------
  2451. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2452. -----------------------------------------------------------------------------------------------------------------------------------------
  2453. BB01 [0000] 1 1 [???..???) i internal label target
  2454. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  2455. BB03 [0005] 1 BB02 0.50 [???..???) internal
  2456. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target
  2457. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i
  2458. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target
  2459. -----------------------------------------------------------------------------------------------------------------------------------------
  2460.  
  2461. ------------ BB01 [???..???), preds={} succs={BB02}
  2462.  
  2463. ***** BB01
  2464. STMT00000 (IL ???... ???)
  2465. N001 ( 0, 0) [000000] ------------ * NOP void
  2466.  
  2467. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2468.  
  2469. ***** BB02
  2470. STMT00007 (IL ???... ???)
  2471. N005 ( 9, 16) [000022] ------------ * JTRUE void
  2472. N004 ( 7, 14) [000016] J------N---- \--* EQ int
  2473. N002 ( 5, 12) [000014] n----------- +--* IND int
  2474. N001 ( 3, 10) [000013] ------------ | \--* CNS_INT(h) long 0x7fff4561eaf0 token
  2475. N003 ( 1, 1) [000015] ------------ \--* CNS_INT int 0
  2476.  
  2477. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2478.  
  2479. ***** BB03
  2480. STMT00008 (IL ???... ???)
  2481. N001 ( 14, 5) [000017] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2482.  
  2483. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2484.  
  2485. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2486.  
  2487. ***** BB05
  2488. STMT00001 (IL 0x000...0x000)
  2489. N001 ( 1, 1) [000001] ------------ * NO_OP void
  2490.  
  2491. ***** BB05
  2492. STMT00002 (IL 0x001...0x004)
  2493. N004 ( 6, 5) [000005] -A------R--- * ASG simd16 (copy)
  2494. N003 ( 3, 2) [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2495. N002 ( 2, 2) [000021] ------------ \--* SIMD simd16 double init
  2496. N001 ( 1, 1) [000004] ------------ \--* CNS_INT int 0
  2497.  
  2498. ***** BB05
  2499. STMT00003 (IL 0x009...0x00A)
  2500. N003 ( 7, 5) [000009] -A------R--- * ASG simd16 (copy)
  2501. N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2502. N001 ( 3, 2) [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2503.  
  2504. ***** BB05
  2505. STMT00004 (IL 0x00B...0x00B)
  2506. N001 ( 0, 0) [000010] ------------ * NOP void
  2507.  
  2508. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2509.  
  2510. ***** BB06
  2511. STMT00005 (IL 0x00D...0x00E)
  2512. N002 ( 4, 3) [000012] ------------ * RETURN simd16
  2513. N001 ( 3, 2) [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2514.  
  2515. -------------------------------------------------------------------------------------------------------------------
  2516. rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
  2517. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2518.  
  2519. rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
  2520. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2521.  
  2522. *************** Exiting IR Rationalize
  2523. Trees after IR Rationalize
  2524.  
  2525. -----------------------------------------------------------------------------------------------------------------------------------------
  2526. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2527. -----------------------------------------------------------------------------------------------------------------------------------------
  2528. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2529. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2530. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2531. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2532. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2533. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2534. -----------------------------------------------------------------------------------------------------------------------------------------
  2535.  
  2536. ------------ BB01 [???..???), preds={} succs={BB02}
  2537. N001 ( 0, 0) [000000] ------------ NOP void
  2538.  
  2539. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2540. N001 ( 3, 10) [000013] ------------ t13 = CNS_INT(h) long 0x7fff4561eaf0 token
  2541. /--* t13 long
  2542. N002 ( 5, 12) [000014] n----------- t14 = * IND int
  2543. N003 ( 1, 1) [000015] ------------ t15 = CNS_INT int 0
  2544. /--* t14 int
  2545. +--* t15 int
  2546. N004 ( 7, 14) [000016] J------N---- t16 = * EQ int
  2547. /--* t16 int
  2548. N005 ( 9, 16) [000022] ------------ * JTRUE void
  2549.  
  2550. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2551. N001 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2552.  
  2553. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2554.  
  2555. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2556. [000023] ------------ IL_OFFSET void IL offset: 0x0
  2557. N001 ( 1, 1) [000001] ------------ NO_OP void
  2558. [000024] ------------ IL_OFFSET void IL offset: 0x1
  2559. N001 ( 1, 1) [000004] ------------ t4 = CNS_INT int 0
  2560. /--* t4 int
  2561. N002 ( 2, 2) [000021] ------------ t21 = * SIMD simd16 double init
  2562. /--* t21 simd16
  2563. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2564. [000025] ------------ IL_OFFSET void IL offset: 0x9
  2565. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2566. /--* t6 simd16
  2567. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2568. [000026] ------------ IL_OFFSET void IL offset: 0xb
  2569. N001 ( 0, 0) [000010] ------------ NOP void
  2570.  
  2571. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2572. [000027] ------------ IL_OFFSET void IL offset: 0xd
  2573. N001 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2574. /--* t11 simd16
  2575. N002 ( 4, 3) [000012] ------------ * RETURN simd16
  2576.  
  2577. -------------------------------------------------------------------------------------------------------------------
  2578. *************** In fgDebugCheckBBlist
  2579. Bumping outgoingArgSpaceSize to 32 for call [000017]
  2580. *************** In fgDebugCheckBBlist
  2581. *************** In Lowering
  2582. Trees before Lowering
  2583.  
  2584. -----------------------------------------------------------------------------------------------------------------------------------------
  2585. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2586. -----------------------------------------------------------------------------------------------------------------------------------------
  2587. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2588. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2589. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2590. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2591. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2592. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2593. -----------------------------------------------------------------------------------------------------------------------------------------
  2594.  
  2595. ------------ BB01 [???..???), preds={} succs={BB02}
  2596. N001 ( 0, 0) [000000] ------------ NOP void
  2597.  
  2598. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2599. N001 ( 3, 10) [000013] ------------ t13 = CNS_INT(h) long 0x7fff4561eaf0 token
  2600. /--* t13 long
  2601. N002 ( 5, 12) [000014] n----------- t14 = * IND int
  2602. N003 ( 1, 1) [000015] ------------ t15 = CNS_INT int 0
  2603. /--* t14 int
  2604. +--* t15 int
  2605. N004 ( 7, 14) [000016] J------N---- t16 = * EQ int
  2606. /--* t16 int
  2607. N005 ( 9, 16) [000022] ------------ * JTRUE void
  2608.  
  2609. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2610. N001 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2611.  
  2612. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2613.  
  2614. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2615. [000023] ------------ IL_OFFSET void IL offset: 0x0
  2616. N001 ( 1, 1) [000001] ------------ NO_OP void
  2617. [000024] ------------ IL_OFFSET void IL offset: 0x1
  2618. N001 ( 1, 1) [000004] ------------ t4 = CNS_INT int 0
  2619. /--* t4 int
  2620. N002 ( 2, 2) [000021] ------------ t21 = * SIMD simd16 double init
  2621. /--* t21 simd16
  2622. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2623. [000025] ------------ IL_OFFSET void IL offset: 0x9
  2624. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2625. /--* t6 simd16
  2626. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2627. [000026] ------------ IL_OFFSET void IL offset: 0xb
  2628. N001 ( 0, 0) [000010] ------------ NOP void
  2629.  
  2630. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2631. [000027] ------------ IL_OFFSET void IL offset: 0xd
  2632. N001 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2633. /--* t11 simd16
  2634. N002 ( 4, 3) [000012] ------------ * RETURN simd16
  2635.  
  2636. -------------------------------------------------------------------------------------------------------------------
  2637. lowering call (before):
  2638. N001 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2639.  
  2640. objp:
  2641. ======
  2642.  
  2643. args:
  2644. ======
  2645.  
  2646. late:
  2647. ======
  2648. lowering call (after):
  2649. N001 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2650.  
  2651. lowering GT_RETURN
  2652. N002 ( 4, 3) [000012] ------------ * RETURN simd16
  2653. ============Lower has completed modifying nodes.
  2654.  
  2655. -----------------------------------------------------------------------------------------------------------------------------------------
  2656. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2657. -----------------------------------------------------------------------------------------------------------------------------------------
  2658. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2659. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2660. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2661. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2662. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2663. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2664. -----------------------------------------------------------------------------------------------------------------------------------------
  2665.  
  2666. ------------ BB01 [???..???), preds={} succs={BB02}
  2667. N001 ( 0, 0) [000000] ------------ NOP void
  2668.  
  2669. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2670. N001 ( 3, 10) [000013] -c---------- t13 = CNS_INT(h) long 0x7fff4561eaf0 token
  2671. /--* t13 long
  2672. N002 ( 5, 12) [000014] nc---------- t14 = * IND int
  2673. N003 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 0
  2674. /--* t14 int
  2675. +--* t15 int
  2676. N004 ( 7, 14) [000016] J------N---- * EQ void
  2677. N005 ( 9, 16) [000022] ------------ * JTRUE void
  2678.  
  2679. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2680. N001 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2681.  
  2682. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2683.  
  2684. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2685. [000023] ------------ IL_OFFSET void IL offset: 0x0
  2686. N001 ( 1, 1) [000001] ------------ NO_OP void
  2687. [000024] ------------ IL_OFFSET void IL offset: 0x1
  2688. N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0
  2689. /--* t4 int
  2690. N002 ( 2, 2) [000021] ------------ t21 = * SIMD simd16 double init
  2691. /--* t21 simd16
  2692. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2693. [000025] ------------ IL_OFFSET void IL offset: 0x9
  2694. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2695. /--* t6 simd16
  2696. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2697. [000026] ------------ IL_OFFSET void IL offset: 0xb
  2698. N001 ( 0, 0) [000010] ------------ NOP void
  2699.  
  2700. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2701. [000027] ------------ IL_OFFSET void IL offset: 0xd
  2702. N001 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2703. /--* t11 simd16
  2704. N002 ( 4, 3) [000012] ------------ * RETURN simd16
  2705.  
  2706. -------------------------------------------------------------------------------------------------------------------
  2707.  
  2708. *** lvaComputeRefCounts ***
  2709. *************** In fgLocalVarLiveness()
  2710. ; Initial local variable assignments
  2711. ;
  2712. ; V00 loc0 simd16 ld-addr-op
  2713. ; V01 loc1 simd16
  2714. ; V02 OutArgs lclBlk (32) "OutgoingArgSpace"
  2715. In fgLocalVarLivenessInit
  2716. *************** In fgPerBlockLocalVarLiveness()
  2717. *************** In fgInterBlockLocalVarLiveness()
  2718. *************** In fgExtendDbgLifetimes()
  2719.  
  2720. Marking vars alive over their entire scope :
  2721.  
  2722. Local variable scopes = 2
  2723. VarNum LVNum Name Beg End
  2724. Sorted by enter scope:
  2725. 0: 01h 01h V01 loc1 000h 00Fh <-- next enter scope
  2726. 1: 00h 00h V00 loc0 000h 00Fh
  2727. Sorted by exit scope:
  2728. 0: 01h 01h V01 loc1 000h 00Fh <-- next exit scope
  2729. 1: 00h 00h V00 loc0 000h 00Fh
  2730. Scope info: block BB01 marking in scope: {}
  2731. Scope info: block BB02 marking in scope: {}
  2732. Scope info: block BB03 marking in scope: {}
  2733. Scope info: block BB04 marking in scope: {}
  2734. Scope info: block BB05 marking in scope: {}
  2735. Scope info: block BB06 marking in scope: {}
  2736.  
  2737. Debug scopes:
  2738. BB01: {}
  2739. BB02: {}
  2740. BB03: {}
  2741. BB04: {}
  2742. BB05: {}
  2743. BB06: {}
  2744. Scope info: block BB01 UNmarking in scope: {}
  2745.  
  2746. BB liveness after fgExtendDbgLifetimes():
  2747.  
  2748. BB01 IN (0)={} + ByrefExposed + GcHeap
  2749. OUT(0)={} + ByrefExposed + GcHeap
  2750.  
  2751. BB02 IN (0)={} + ByrefExposed + GcHeap
  2752. OUT(0)={} + ByrefExposed + GcHeap
  2753.  
  2754. BB03 IN (0)={} + ByrefExposed + GcHeap
  2755. OUT(0)={} + ByrefExposed + GcHeap
  2756.  
  2757. BB04 IN (0)={} + ByrefExposed + GcHeap
  2758. OUT(0)={} + ByrefExposed + GcHeap
  2759.  
  2760. BB05 IN (0)={} + ByrefExposed + GcHeap
  2761. OUT(0)={} + ByrefExposed + GcHeap
  2762.  
  2763. BB06 IN (0)={} + ByrefExposed + GcHeap
  2764. OUT(0)={} + ByrefExposed + GcHeap
  2765.  
  2766.  
  2767.  
  2768. *** lvaComputeRefCounts ***
  2769. Liveness pass finished after lowering, IR:
  2770.  
  2771. -----------------------------------------------------------------------------------------------------------------------------------------
  2772. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2773. -----------------------------------------------------------------------------------------------------------------------------------------
  2774. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2775. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2776. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2777. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2778. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2779. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2780. -----------------------------------------------------------------------------------------------------------------------------------------
  2781.  
  2782. ------------ BB01 [???..???), preds={} succs={BB02}
  2783. N001 ( 0, 0) [000000] ------------ NOP void
  2784.  
  2785. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2786. N001 ( 3, 10) [000013] -c---------- t13 = CNS_INT(h) long 0x7fff4561eaf0 token
  2787. /--* t13 long
  2788. N002 ( 5, 12) [000014] nc---------- t14 = * IND int
  2789. N003 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 0
  2790. /--* t14 int
  2791. +--* t15 int
  2792. N004 ( 7, 14) [000016] J------N---- * EQ void
  2793. N005 ( 9, 16) [000022] ------------ * JTRUE void
  2794.  
  2795. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2796. N001 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2797.  
  2798. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2799.  
  2800. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2801. [000023] ------------ IL_OFFSET void IL offset: 0x0
  2802. N001 ( 1, 1) [000001] ------------ NO_OP void
  2803. [000024] ------------ IL_OFFSET void IL offset: 0x1
  2804. N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0
  2805. /--* t4 int
  2806. N002 ( 2, 2) [000021] ------------ t21 = * SIMD simd16 double init
  2807. /--* t21 simd16
  2808. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2809. [000025] ------------ IL_OFFSET void IL offset: 0x9
  2810. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2811. /--* t6 simd16
  2812. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2813. [000026] ------------ IL_OFFSET void IL offset: 0xb
  2814. N001 ( 0, 0) [000010] ------------ NOP void
  2815.  
  2816. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2817. [000027] ------------ IL_OFFSET void IL offset: 0xd
  2818. N001 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2819. /--* t11 simd16
  2820. N002 ( 4, 3) [000012] ------------ * RETURN simd16
  2821.  
  2822. -------------------------------------------------------------------------------------------------------------------
  2823. *************** Exiting Lowering
  2824. Trees after Lowering
  2825.  
  2826. -----------------------------------------------------------------------------------------------------------------------------------------
  2827. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2828. -----------------------------------------------------------------------------------------------------------------------------------------
  2829. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2830. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2831. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2832. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2833. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2834. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2835. -----------------------------------------------------------------------------------------------------------------------------------------
  2836.  
  2837. ------------ BB01 [???..???), preds={} succs={BB02}
  2838. N001 ( 0, 0) [000000] ------------ NOP void
  2839.  
  2840. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2841. N001 ( 3, 10) [000013] -c---------- t13 = CNS_INT(h) long 0x7fff4561eaf0 token
  2842. /--* t13 long
  2843. N002 ( 5, 12) [000014] nc---------- t14 = * IND int
  2844. N003 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 0
  2845. /--* t14 int
  2846. +--* t15 int
  2847. N004 ( 7, 14) [000016] J------N---- * EQ void
  2848. N005 ( 9, 16) [000022] ------------ * JTRUE void
  2849.  
  2850. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2851. N001 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2852.  
  2853. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2854.  
  2855. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2856. [000023] ------------ IL_OFFSET void IL offset: 0x0
  2857. N001 ( 1, 1) [000001] ------------ NO_OP void
  2858. [000024] ------------ IL_OFFSET void IL offset: 0x1
  2859. N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0
  2860. /--* t4 int
  2861. N002 ( 2, 2) [000021] ------------ t21 = * SIMD simd16 double init
  2862. /--* t21 simd16
  2863. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2864. [000025] ------------ IL_OFFSET void IL offset: 0x9
  2865. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2866. /--* t6 simd16
  2867. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2868. [000026] ------------ IL_OFFSET void IL offset: 0xb
  2869. N001 ( 0, 0) [000010] ------------ NOP void
  2870.  
  2871. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2872. [000027] ------------ IL_OFFSET void IL offset: 0xd
  2873. N001 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2874. /--* t11 simd16
  2875. N002 ( 4, 3) [000012] ------------ * RETURN simd16
  2876.  
  2877. -------------------------------------------------------------------------------------------------------------------
  2878. *************** In fgDebugCheckBBlist
  2879. *************** In StackLevelSetter
  2880. Trees before StackLevelSetter
  2881.  
  2882. -----------------------------------------------------------------------------------------------------------------------------------------
  2883. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2884. -----------------------------------------------------------------------------------------------------------------------------------------
  2885. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2886. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2887. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2888. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2889. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2890. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2891. -----------------------------------------------------------------------------------------------------------------------------------------
  2892.  
  2893. ------------ BB01 [???..???), preds={} succs={BB02}
  2894. N001 ( 0, 0) [000000] ------------ NOP void
  2895.  
  2896. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2897. N001 ( 3, 10) [000013] -c---------- t13 = CNS_INT(h) long 0x7fff4561eaf0 token
  2898. /--* t13 long
  2899. N002 ( 5, 12) [000014] nc---------- t14 = * IND int
  2900. N003 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 0
  2901. /--* t14 int
  2902. +--* t15 int
  2903. N004 ( 7, 14) [000016] J------N---- * EQ void
  2904. N005 ( 9, 16) [000022] ------------ * JTRUE void
  2905.  
  2906. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2907. N001 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2908.  
  2909. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2910.  
  2911. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2912. [000023] ------------ IL_OFFSET void IL offset: 0x0
  2913. N001 ( 1, 1) [000001] ------------ NO_OP void
  2914. [000024] ------------ IL_OFFSET void IL offset: 0x1
  2915. N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0
  2916. /--* t4 int
  2917. N002 ( 2, 2) [000021] ------------ t21 = * SIMD simd16 double init
  2918. /--* t21 simd16
  2919. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2920. [000025] ------------ IL_OFFSET void IL offset: 0x9
  2921. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2922. /--* t6 simd16
  2923. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2924. [000026] ------------ IL_OFFSET void IL offset: 0xb
  2925. N001 ( 0, 0) [000010] ------------ NOP void
  2926.  
  2927. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2928. [000027] ------------ IL_OFFSET void IL offset: 0xd
  2929. N001 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2930. /--* t11 simd16
  2931. N002 ( 4, 3) [000012] ------------ * RETURN simd16
  2932.  
  2933. -------------------------------------------------------------------------------------------------------------------
  2934. *************** Exiting StackLevelSetter
  2935. Trees after StackLevelSetter
  2936.  
  2937. -----------------------------------------------------------------------------------------------------------------------------------------
  2938. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2939. -----------------------------------------------------------------------------------------------------------------------------------------
  2940. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2941. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2942. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2943. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2944. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2945. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2946. -----------------------------------------------------------------------------------------------------------------------------------------
  2947.  
  2948. ------------ BB01 [???..???), preds={} succs={BB02}
  2949. N001 ( 0, 0) [000000] ------------ NOP void
  2950.  
  2951. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2952. N001 ( 3, 10) [000013] -c---------- t13 = CNS_INT(h) long 0x7fff4561eaf0 token
  2953. /--* t13 long
  2954. N002 ( 5, 12) [000014] nc---------- t14 = * IND int
  2955. N003 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 0
  2956. /--* t14 int
  2957. +--* t15 int
  2958. N004 ( 7, 14) [000016] J------N---- * EQ void
  2959. N005 ( 9, 16) [000022] ------------ * JTRUE void
  2960.  
  2961. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2962. N001 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2963.  
  2964. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2965.  
  2966. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2967. [000023] ------------ IL_OFFSET void IL offset: 0x0
  2968. N001 ( 1, 1) [000001] ------------ NO_OP void
  2969. [000024] ------------ IL_OFFSET void IL offset: 0x1
  2970. N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0
  2971. /--* t4 int
  2972. N002 ( 2, 2) [000021] ------------ t21 = * SIMD simd16 double init
  2973. /--* t21 simd16
  2974. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2975. [000025] ------------ IL_OFFSET void IL offset: 0x9
  2976. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0
  2977. /--* t6 simd16
  2978. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2979. [000026] ------------ IL_OFFSET void IL offset: 0xb
  2980. N001 ( 0, 0) [000010] ------------ NOP void
  2981.  
  2982. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2983. [000027] ------------ IL_OFFSET void IL offset: 0xd
  2984. N001 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1
  2985. /--* t11 simd16
  2986. N002 ( 4, 3) [000012] ------------ * RETURN simd16
  2987.  
  2988. -------------------------------------------------------------------------------------------------------------------
  2989. *************** In fgDebugCheckBBlist
  2990. Clearing modified regs.
  2991.  
  2992. buildIntervals ========
  2993.  
  2994. -----------------
  2995. LIVENESS:
  2996. -----------------
  2997. BB01 use def in out
  2998. {}
  2999. {}
  3000. {}
  3001. {}
  3002. BB02 use def in out
  3003. {}
  3004. {}
  3005. {}
  3006. {}
  3007. BB03 use def in out
  3008. {}
  3009. {}
  3010. {}
  3011. {}
  3012. BB04 use def in out
  3013. {}
  3014. {}
  3015. {}
  3016. {}
  3017. BB05 use def in out
  3018. {}
  3019. {}
  3020. {}
  3021. {}
  3022. BB06 use def in out
  3023. {}
  3024. {}
  3025. {}
  3026. {}
  3027.  
  3028. FP callee save candidate vars: None
  3029.  
  3030. floatVarCount = 0; hasLoops = 0, singleExit = 1
  3031. TUPLE STYLE DUMP BEFORE LSRA
  3032. LSRA Block Sequence: BB01( 1 )
  3033. BB02( 1 )
  3034. BB03( 0.50)
  3035. BB04( 1 )
  3036. BB05( 1 )
  3037. BB06( 1 )
  3038.  
  3039. BB01 [???..???), preds={} succs={BB02}
  3040. =====
  3041. N001. NOP
  3042.  
  3043. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  3044. =====
  3045. N001. CNS_INT(h) 0x7fff4561eaf0 token
  3046. N002. IND
  3047. N003. CNS_INT 0
  3048. N004. EQ
  3049. N005. JTRUE
  3050.  
  3051. BB03 [???..???), preds={BB02} succs={BB04}
  3052. =====
  3053. N001. CALL help
  3054.  
  3055. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  3056. =====
  3057.  
  3058. BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  3059. =====
  3060. N000. IL_OFFSET IL offset: 0x0
  3061. N001. NO_OP
  3062. N000. IL_OFFSET IL offset: 0x1
  3063. N001. CNS_INT 0
  3064. N002. t21 = SIMD
  3065. N004. V00 MEM; t21
  3066. N000. IL_OFFSET IL offset: 0x9
  3067. N001. t6 = V00 MEM
  3068. N003. V01 MEM; t6
  3069. N000. IL_OFFSET IL offset: 0xb
  3070. N001. NOP
  3071.  
  3072. BB06 [00D..00F) (return), preds={BB05} succs={}
  3073. =====
  3074. N000. IL_OFFSET IL offset: 0xd
  3075. N001. t11 = V01 MEM
  3076. N002. RETURN ; t11
  3077.  
  3078.  
  3079.  
  3080.  
  3081. buildIntervals second part ========
  3082.  
  3083. NEW BLOCK BB01
  3084. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  3085.  
  3086. DefList: { }
  3087. N002 ( 0, 0) [000000] ------------ * NOP void REG NA
  3088.  
  3089.  
  3090. NEW BLOCK BB02
  3091.  
  3092.  
  3093. Setting BB01 as the predecessor for determining incoming variable registers of BB02
  3094. <RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
  3095.  
  3096. DefList: { }
  3097. N006 ( 3, 10) [000013] -c---------- * CNS_INT(h) long 0x7fff4561eaf0 token REG NA
  3098. Contained
  3099. DefList: { }
  3100. N008 ( 5, 12) [000014] nc---------- * IND int REG NA
  3101. Contained
  3102. DefList: { }
  3103. N010 ( 1, 1) [000015] -c---------- * CNS_INT int 0 REG NA
  3104. Contained
  3105. DefList: { }
  3106. N012 ( 7, 14) [000016] J------N---- * EQ void REG NA
  3107.  
  3108. DefList: { }
  3109. N014 ( 9, 16) [000022] ------------ * JTRUE void REG NA
  3110.  
  3111.  
  3112. NEW BLOCK BB03
  3113.  
  3114.  
  3115. Setting BB02 as the predecessor for determining incoming variable registers of BB03
  3116. <RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
  3117.  
  3118. DefList: { }
  3119. N018 ( 14, 5) [000017] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  3120. <RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1>
  3121. <RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1>
  3122. <RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1>
  3123. <RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1>
  3124. <RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1>
  3125. <RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1>
  3126. <RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1>
  3127. <RefPosition #10 @19 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1>
  3128. <RefPosition #11 @19 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1>
  3129. <RefPosition #12 @19 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1>
  3130. <RefPosition #13 @19 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1>
  3131. <RefPosition #14 @19 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1>
  3132. <RefPosition #15 @19 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1>
  3133.  
  3134.  
  3135. NEW BLOCK BB04
  3136.  
  3137.  
  3138. Setting BB02 as the predecessor for determining incoming variable registers of BB04
  3139. <RefPosition #16 @20 RefTypeBB BB04 regmask=[] minReg=1>
  3140.  
  3141.  
  3142. NEW BLOCK BB05
  3143.  
  3144.  
  3145. Setting BB04 as the predecessor for determining incoming variable registers of BB05
  3146. <RefPosition #17 @22 RefTypeBB BB05 regmask=[] minReg=1>
  3147.  
  3148. DefList: { }
  3149. N024 (???,???) [000023] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
  3150.  
  3151. DefList: { }
  3152. N026 ( 1, 1) [000001] ------------ * NO_OP void REG NA
  3153.  
  3154. DefList: { }
  3155. N028 (???,???) [000024] ------------ * IL_OFFSET void IL offset: 0x1 REG NA
  3156.  
  3157. DefList: { }
  3158. N030 ( 1, 1) [000004] -c---------- * CNS_INT int 0 REG NA
  3159. Contained
  3160. DefList: { }
  3161. N032 ( 2, 2) [000021] ------------ * SIMD simd16 double init REG NA
  3162. Interval 0: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
  3163. <RefPosition #18 @33 RefTypeDef <Ivl:0> SIMD BB05 regmask=[allFloat] minReg=1>
  3164.  
  3165. DefList: { N032.t21. SIMD }
  3166. N034 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0 NA REG NA
  3167. <RefPosition #19 @34 RefTypeUse <Ivl:0> BB05 regmask=[allFloat] minReg=1 last>
  3168.  
  3169. DefList: { }
  3170. N036 (???,???) [000025] ------------ * IL_OFFSET void IL offset: 0x9 REG NA
  3171.  
  3172. DefList: { }
  3173. N038 ( 3, 2) [000006] ------------ * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0 NA REG NA
  3174. Interval 1: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
  3175. <RefPosition #20 @39 RefTypeDef <Ivl:1> LCL_VAR BB05 regmask=[allFloat] minReg=1>
  3176.  
  3177. DefList: { N038.t6. LCL_VAR }
  3178. N040 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1 NA REG NA
  3179. <RefPosition #21 @40 RefTypeUse <Ivl:1> BB05 regmask=[allFloat] minReg=1 last>
  3180.  
  3181. DefList: { }
  3182. N042 (???,???) [000026] ------------ * IL_OFFSET void IL offset: 0xb REG NA
  3183.  
  3184. DefList: { }
  3185. N044 ( 0, 0) [000010] ------------ * NOP void REG NA
  3186.  
  3187.  
  3188. NEW BLOCK BB06
  3189.  
  3190.  
  3191. Setting BB05 as the predecessor for determining incoming variable registers of BB06
  3192. <RefPosition #22 @46 RefTypeBB BB06 regmask=[] minReg=1>
  3193.  
  3194. DefList: { }
  3195. N048 (???,???) [000027] ------------ * IL_OFFSET void IL offset: 0xd REG NA
  3196.  
  3197. DefList: { }
  3198. N050 ( 3, 2) [000011] ------------ * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1 NA REG NA
  3199. Interval 2: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
  3200. <RefPosition #23 @51 RefTypeDef <Ivl:2> LCL_VAR BB06 regmask=[allFloat] minReg=1>
  3201.  
  3202. DefList: { N050.t11. LCL_VAR }
  3203. N052 ( 4, 3) [000012] ------------ * RETURN simd16 REG NA
  3204. <RefPosition #24 @52 RefTypeFixedReg <Reg:mm0> BB06 regmask=[mm0] minReg=1>
  3205. <RefPosition #25 @52 RefTypeUse <Ivl:2> BB06 regmask=[mm0] minReg=1 last fixed>
  3206.  
  3207.  
  3208. Linear scan intervals BEFORE VALIDATING INTERVALS:
  3209. Interval 0: simd16 RefPositions {#18@33 #19@34} physReg:NA Preferences=[allFloat]
  3210. Interval 1: simd16 RefPositions {#20@39 #21@40} physReg:NA Preferences=[allFloat]
  3211. Interval 2: simd16 RefPositions {#23@51 #25@52} physReg:NA Preferences=[mm0]
  3212.  
  3213. ------------
  3214. REFPOSITIONS BEFORE VALIDATING INTERVALS:
  3215. ------------
  3216. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  3217. <RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
  3218. <RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
  3219. <RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  3220. <RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  3221. <RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  3222. <RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  3223. <RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  3224. <RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  3225. <RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  3226. <RefPosition #10 @19 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  3227. <RefPosition #11 @19 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  3228. <RefPosition #12 @19 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  3229. <RefPosition #13 @19 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  3230. <RefPosition #14 @19 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  3231. <RefPosition #15 @19 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  3232. <RefPosition #16 @20 RefTypeBB BB04 regmask=[] minReg=1>
  3233. <RefPosition #17 @22 RefTypeBB BB05 regmask=[] minReg=1>
  3234. <RefPosition #18 @33 RefTypeDef <Ivl:0> SIMD BB05 regmask=[allFloat] minReg=1>
  3235. <RefPosition #19 @34 RefTypeUse <Ivl:0> BB05 regmask=[allFloat] minReg=1 last>
  3236. <RefPosition #20 @39 RefTypeDef <Ivl:1> LCL_VAR BB05 regmask=[allFloat] minReg=1>
  3237. <RefPosition #21 @40 RefTypeUse <Ivl:1> BB05 regmask=[allFloat] minReg=1 last>
  3238. <RefPosition #22 @46 RefTypeBB BB06 regmask=[] minReg=1>
  3239. <RefPosition #23 @51 RefTypeDef <Ivl:2> LCL_VAR BB06 regmask=[mm0] minReg=1>
  3240. <RefPosition #24 @52 RefTypeFixedReg <Reg:mm0> BB06 regmask=[mm0] minReg=1>
  3241. <RefPosition #25 @52 RefTypeUse <Ivl:2> BB06 regmask=[mm0] minReg=1 last fixed>
  3242. TUPLE STYLE DUMP WITH REF POSITIONS
  3243. Incoming Parameters:
  3244. BB01 [???..???), preds={} succs={BB02}
  3245. =====
  3246. N002. NOP
  3247.  
  3248. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  3249. =====
  3250. N006. CNS_INT(h) 0x7fff4561eaf0 token
  3251. N008. IND
  3252. N010. CNS_INT 0
  3253. N012. EQ
  3254. N014. JTRUE
  3255.  
  3256. BB03 [???..???), preds={BB02} succs={BB04}
  3257. =====
  3258. N018. CALL help
  3259. Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5
  3260.  
  3261. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  3262. =====
  3263.  
  3264. BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  3265. =====
  3266. N024. IL_OFFSET IL offset: 0x0
  3267. N026. NO_OP
  3268. N028. IL_OFFSET IL offset: 0x1
  3269. N030. CNS_INT 0
  3270. N032. SIMD
  3271. Def:<I0>(#18)
  3272. N034. V00 MEM
  3273. Use:<I0>(#19) *
  3274. N036. IL_OFFSET IL offset: 0x9
  3275. N038. V00 MEM
  3276. Def:<I1>(#20)
  3277. N040. V01 MEM
  3278. Use:<I1>(#21) *
  3279. N042. IL_OFFSET IL offset: 0xb
  3280. N044. NOP
  3281.  
  3282. BB06 [00D..00F) (return), preds={BB05} succs={}
  3283. =====
  3284. N048. IL_OFFSET IL offset: 0xd
  3285. N050. V01 MEM
  3286. Def:<I2>(#23)
  3287. N052. RETURN
  3288. Use:<I2>(#25) Fixed:mm0(#24) *
  3289.  
  3290.  
  3291.  
  3292.  
  3293. Linear scan intervals after buildIntervals:
  3294. Interval 0: simd16 RefPositions {#18@33 #19@34} physReg:NA Preferences=[allFloat]
  3295. Interval 1: simd16 RefPositions {#20@39 #21@40} physReg:NA Preferences=[allFloat]
  3296. Interval 2: simd16 RefPositions {#23@51 #25@52} physReg:NA Preferences=[mm0]
  3297.  
  3298. *************** In LinearScan::allocateRegisters()
  3299.  
  3300. Linear scan intervals before allocateRegisters:
  3301. Interval 0: simd16 RefPositions {#18@33 #19@34} physReg:NA Preferences=[allFloat]
  3302. Interval 1: simd16 RefPositions {#20@39 #21@40} physReg:NA Preferences=[allFloat]
  3303. Interval 2: simd16 RefPositions {#23@51 #25@52} physReg:NA Preferences=[mm0]
  3304.  
  3305. ------------
  3306. REFPOSITIONS BEFORE ALLOCATION:
  3307. ------------
  3308. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  3309. <RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
  3310. <RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
  3311. <RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  3312. <RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  3313. <RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  3314. <RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  3315. <RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  3316. <RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  3317. <RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  3318. <RefPosition #10 @19 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  3319. <RefPosition #11 @19 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  3320. <RefPosition #12 @19 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  3321. <RefPosition #13 @19 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  3322. <RefPosition #14 @19 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  3323. <RefPosition #15 @19 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  3324. <RefPosition #16 @20 RefTypeBB BB04 regmask=[] minReg=1>
  3325. <RefPosition #17 @22 RefTypeBB BB05 regmask=[] minReg=1>
  3326. <RefPosition #18 @33 RefTypeDef <Ivl:0> SIMD BB05 regmask=[allFloat] minReg=1>
  3327. <RefPosition #19 @34 RefTypeUse <Ivl:0> BB05 regmask=[allFloat] minReg=1 last>
  3328. <RefPosition #20 @39 RefTypeDef <Ivl:1> LCL_VAR BB05 regmask=[allFloat] minReg=1>
  3329. <RefPosition #21 @40 RefTypeUse <Ivl:1> BB05 regmask=[allFloat] minReg=1 last>
  3330. <RefPosition #22 @46 RefTypeBB BB06 regmask=[] minReg=1>
  3331. <RefPosition #23 @51 RefTypeDef <Ivl:2> LCL_VAR BB06 regmask=[mm0] minReg=1>
  3332. <RefPosition #24 @52 RefTypeFixedReg <Reg:mm0> BB06 regmask=[mm0] minReg=1>
  3333. <RefPosition #25 @52 RefTypeUse <Ivl:2> BB06 regmask=[mm0] minReg=1 last fixed>
  3334.  
  3335.  
  3336. Allocating Registers
  3337. --------------------
  3338. The following table has one or more rows for each RefPosition that is handled during allocation.
  3339. The first column provides the basic information about the RefPosition, with its type (e.g. Def,
  3340. Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
  3341. action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
  3342. The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
  3343. active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
  3344. Columns are only printed up to the last modifed register, which may increase during allocation,
  3345. in which case additional columns will appear.
  3346. Registers which are not marked modified have ---- in their column.
  3347.  
  3348. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3349. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3350. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3351. | | | | | | | | | | | | | | |
  3352. 0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
  3353. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3354. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3355. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3356. 4.#1 BB2 PredBB1 | | | | | | | | | | | | | | |
  3357. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3358. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3359. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3360. 16.#2 BB3 PredBB2 | | | | | | | | | | | | | | |
  3361. 19.#3 rax Kill Keep rax | | | | | | | | | | | | | | |
  3362. 19.#4 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  3363. 19.#5 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  3364. 19.#6 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  3365. 19.#7 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  3366. 19.#8 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  3367. 19.#9 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  3368. 19.#10 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  3369. 19.#11 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  3370. 19.#12 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  3371. 19.#13 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  3372. 19.#14 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  3373. 19.#15 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  3374. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3375. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3376. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3377. 20.#16 BB4 PredBB2 | | | | | | | | | | | | | | |
  3378. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3379. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3380. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3381. 22.#17 BB5 PredBB4 | | | | | | | | | | | | | | |
  3382. 33.#18 I0 Def Alloc mm0 | | | | | | | | | |I0 a| | | | |
  3383. 34.#19 I0 Use * Keep mm0 | | | | | | | | | |I0 a| | | | |
  3384. 39.#20 I1 Def Alloc mm0 | | | | | | | | | |I1 a| | | | |
  3385. 40.#21 I1 Use * Keep mm0 | | | | | | | | | |I1 a| | | | |
  3386. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3387. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3388. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3389. 46.#22 BB6 PredBB5 | | | | | | | | | | | | | | |
  3390. 51.#23 I2 Def Alloc mm0 | | | | | | | | | |I2 a| | | | |
  3391. 52.#24 mm0 Fixd Keep mm0 | | | | | | | | | |I2 a| | | | |
  3392. 52.#25 I2 Use * Keep mm0 | | | | | | | | | | | | | | |
  3393.  
  3394. ------------
  3395. REFPOSITIONS AFTER ALLOCATION:
  3396. ------------
  3397. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  3398. <RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
  3399. <RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
  3400. <RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  3401. <RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  3402. <RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  3403. <RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  3404. <RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  3405. <RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  3406. <RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  3407. <RefPosition #10 @19 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  3408. <RefPosition #11 @19 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  3409. <RefPosition #12 @19 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  3410. <RefPosition #13 @19 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  3411. <RefPosition #14 @19 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  3412. <RefPosition #15 @19 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  3413. <RefPosition #16 @20 RefTypeBB BB04 regmask=[] minReg=1>
  3414. <RefPosition #17 @22 RefTypeBB BB05 regmask=[] minReg=1>
  3415. <RefPosition #18 @33 RefTypeDef <Ivl:0> SIMD BB05 regmask=[mm0] minReg=1>
  3416. <RefPosition #19 @34 RefTypeUse <Ivl:0> BB05 regmask=[mm0] minReg=1 last>
  3417. <RefPosition #20 @39 RefTypeDef <Ivl:1> LCL_VAR BB05 regmask=[mm0] minReg=1>
  3418. <RefPosition #21 @40 RefTypeUse <Ivl:1> BB05 regmask=[mm0] minReg=1 last>
  3419. <RefPosition #22 @46 RefTypeBB BB06 regmask=[] minReg=1>
  3420. <RefPosition #23 @51 RefTypeDef <Ivl:2> LCL_VAR BB06 regmask=[mm0] minReg=1>
  3421. <RefPosition #24 @52 RefTypeFixedReg <Reg:mm0> BB06 regmask=[mm0] minReg=1>
  3422. <RefPosition #25 @52 RefTypeUse <Ivl:2> BB06 regmask=[mm0] minReg=1 last fixed>
  3423. Active intervals at end of allocation:
  3424.  
  3425. Trees after linear scan register allocator (LSRA)
  3426.  
  3427. -----------------------------------------------------------------------------------------------------------------------------------------
  3428. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  3429. -----------------------------------------------------------------------------------------------------------------------------------------
  3430. BB01 [0000] 1 1 [???..???) i internal label target LIR
  3431. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  3432. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  3433. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  3434. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  3435. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  3436. -----------------------------------------------------------------------------------------------------------------------------------------
  3437.  
  3438. ------------ BB01 [???..???), preds={} succs={BB02}
  3439. N002 ( 0, 0) [000000] ------------ NOP void REG NA
  3440.  
  3441. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  3442. N006 ( 3, 10) [000013] -c---------- t13 = CNS_INT(h) long 0x7fff4561eaf0 token REG NA
  3443. /--* t13 long
  3444. N008 ( 5, 12) [000014] nc---------- t14 = * IND int REG NA
  3445. N010 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 0 REG NA
  3446. /--* t14 int
  3447. +--* t15 int
  3448. N012 ( 7, 14) [000016] J------N---- * EQ void REG NA
  3449. N014 ( 9, 16) [000022] ------------ * JTRUE void REG NA
  3450.  
  3451. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  3452. N018 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  3453.  
  3454. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  3455.  
  3456. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  3457. N024 (???,???) [000023] ------------ IL_OFFSET void IL offset: 0x0 REG NA
  3458. N026 ( 1, 1) [000001] ------------ NO_OP void REG NA
  3459. N028 (???,???) [000024] ------------ IL_OFFSET void IL offset: 0x1 REG NA
  3460. N030 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 REG NA
  3461. /--* t4 int
  3462. N032 ( 2, 2) [000021] ------------ t21 = * SIMD simd16 double init REG mm0
  3463. /--* t21 simd16
  3464. N034 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0 NA REG NA
  3465. N036 (???,???) [000025] ------------ IL_OFFSET void IL offset: 0x9 REG NA
  3466. N038 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0 mm0 REG mm0
  3467. /--* t6 simd16
  3468. N040 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1 NA REG NA
  3469. N042 (???,???) [000026] ------------ IL_OFFSET void IL offset: 0xb REG NA
  3470. N044 ( 0, 0) [000010] ------------ NOP void REG NA
  3471.  
  3472. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  3473. N048 (???,???) [000027] ------------ IL_OFFSET void IL offset: 0xd REG NA
  3474. N050 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1 mm0 REG mm0
  3475. /--* t11 simd16
  3476. N052 ( 4, 3) [000012] ------------ * RETURN simd16 REG NA
  3477.  
  3478. -------------------------------------------------------------------------------------------------------------------
  3479.  
  3480. Final allocation
  3481. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3482. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3483. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3484. 0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
  3485. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3486. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3487. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3488. 4.#1 BB2 PredBB1 | | | | | | | | | | | | | | |
  3489. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3490. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3491. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3492. 16.#2 BB3 PredBB2 | | | | | | | | | | | | | | |
  3493. 19.#3 rax Kill Keep rax | | | | | | | | | | | | | | |
  3494. 19.#4 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  3495. 19.#5 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  3496. 19.#6 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  3497. 19.#7 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  3498. 19.#8 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  3499. 19.#9 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  3500. 19.#10 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  3501. 19.#11 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  3502. 19.#12 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  3503. 19.#13 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  3504. 19.#14 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  3505. 19.#15 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  3506. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3507. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3508. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3509. 20.#16 BB4 PredBB2 | | | | | | | | | | | | | | |
  3510. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3511. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3512. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3513. 22.#17 BB5 PredBB4 | | | | | | | | | | | | | | |
  3514. 33.#18 I0 Def Alloc mm0 | | | | | | | | | |I0 a| | | | |
  3515. 34.#19 I0 Use * Keep mm0 | | | | | | | | | |I0 i| | | | |
  3516. 39.#20 I1 Def Alloc mm0 | | | | | | | | | |I1 a| | | | |
  3517. 40.#21 I1 Use * Keep mm0 | | | | | | | | | |I1 i| | | | |
  3518. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3519. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3520. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3521. 46.#22 BB6 PredBB5 | | | | | | | | | | | | | | |
  3522. 51.#23 I2 Def Alloc mm0 | | | | | | | | | |I2 a| | | | |
  3523. 52.#24 mm0 Fixd Keep mm0 | | | | | | | | | |I2 a| | | | |
  3524. 52.#25 I2 Use * Keep mm0 | | | | | | | | | |I2 i| | | | |
  3525.  
  3526. Recording the maximum number of concurrent spills:
  3527.  
  3528. ----------
  3529. LSRA Stats
  3530. ----------
  3531. Total Tracked Vars: 0
  3532. Total Reg Cand Vars: 0
  3533. Total number of Intervals: 2
  3534. Total number of RefPositions: 25
  3535. Total Spill Count: 0 Weighted: 0
  3536. Total CopyReg Count: 0 Weighted: 0
  3537. Total ResolutionMov Count: 0 Weighted: 0
  3538. Total number of split edges: 0
  3539. Total Number of spill temps created: 0
  3540.  
  3541. TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
  3542. Incoming Parameters:
  3543. BB01 [???..???), preds={} succs={BB02}
  3544. =====
  3545. N002. NOP
  3546.  
  3547. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  3548. =====
  3549. N006. CNS_INT(h) 0x7fff4561eaf0 token
  3550. N008. IND
  3551. N010. CNS_INT 0
  3552. N012. EQ
  3553. N014. JTRUE
  3554.  
  3555. BB03 [???..???), preds={BB02} succs={BB04}
  3556. =====
  3557. N018. CALL help
  3558.  
  3559. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  3560. =====
  3561.  
  3562. BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  3563. =====
  3564. N024. IL_OFFSET IL offset: 0x0
  3565. N026. NO_OP
  3566. N028. IL_OFFSET IL offset: 0x1
  3567. N030. CNS_INT 0
  3568. N032. mm0 = SIMD
  3569. N034. V00 MEM; mm0
  3570. N036. IL_OFFSET IL offset: 0x9
  3571. N038. mm0 = V00 MEM
  3572. N040. V01 MEM; mm0
  3573. N042. IL_OFFSET IL offset: 0xb
  3574. N044. NOP
  3575.  
  3576. BB06 [00D..00F) (return), preds={BB05} succs={}
  3577. =====
  3578. N048. IL_OFFSET IL offset: 0xd
  3579. N050. mm0 = V01 MEM
  3580. N052. RETURN ; mm0
  3581.  
  3582.  
  3583.  
  3584. *************** In genGenerateCode()
  3585.  
  3586. -----------------------------------------------------------------------------------------------------------------------------------------
  3587. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  3588. -----------------------------------------------------------------------------------------------------------------------------------------
  3589. BB01 [0000] 1 1 [???..???) i internal label target LIR
  3590. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  3591. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  3592. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  3593. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  3594. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  3595. -----------------------------------------------------------------------------------------------------------------------------------------
  3596. *************** In fgDebugCheckBBlist
  3597. Finalizing stack frame
  3598. Modified regs: [rax rcx rdx r8-r11 mm0-mm5]
  3599. Callee-saved registers pushed: 0 []
  3600. *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
  3601. Pad V00 loc0, size=16, stkOffs=-0x10, pad=0
  3602. Assign V00 loc0, size=16, stkOffs=-0x20
  3603. Pad V01 loc1, size=16, stkOffs=-0x20, pad=0
  3604. Assign V01 loc1, size=16, stkOffs=-0x30
  3605. Assign V02 OutArgs, size=32, stkOffs=-0x50
  3606. ; Final local variable assignments
  3607. ;
  3608. ; V00 loc0 [V00 ] ( 1, 1 ) simd16 -> [rbp-0x10] must-init ld-addr-op
  3609. ; V01 loc1 [V01 ] ( 1, 1 ) simd16 -> [rbp-0x20] must-init
  3610. ; V02 OutArgs [V02 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
  3611. ;
  3612. ; Lcl frame size = 64
  3613. Setting stack level from -572662307 to 0
  3614.  
  3615. =============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000004.40030060: i internal label target LIR
  3616. BB01 IN (0)={} + ByrefExposed + GcHeap
  3617. OUT(0)={} + ByrefExposed + GcHeap
  3618.  
  3619. Liveness not changing: 0000000000000000 {}
  3620. Live regs: (unchanged) 00000000 {}
  3621. GC regs: (unchanged) 00000000 {}
  3622. Byref regs: (unchanged) 00000000 {}
  3623.  
  3624. L_M60652_BB01:
  3625. Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  3626.  
  3627. Scope info: begin block BB01, IL range [???..???)
  3628. Scope info: ignoring block beginning
  3629. Generating: N002 ( 0, 0) [000000] ------------ NOP void REG NA
  3630.  
  3631. Scope info: end block BB01, IL range [???..???)
  3632. Scope info: ignoring block end
  3633.  
  3634. =============== Generating BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.40000040: internal LIR
  3635. BB02 IN (0)={} + ByrefExposed + GcHeap
  3636. OUT(0)={} + ByrefExposed + GcHeap
  3637.  
  3638. Liveness not changing: 0000000000000000 {}
  3639. Live regs: (unchanged) 00000000 {}
  3640. GC regs: (unchanged) 00000000 {}
  3641. Byref regs: (unchanged) 00000000 {}
  3642.  
  3643. L_M60652_BB02:
  3644.  
  3645. Scope info: begin block BB02, IL range [???..???)
  3646. Scope info: ignoring block beginning
  3647. Added IP mapping: NO_MAP STACK_EMPTY (G_M60652_IG02,ins#0,ofs#0) label
  3648. Generating: N006 ( 3, 10) [000013] -c---------- t13 = CNS_INT(h) long 0x7fff4561eaf0 token REG NA
  3649. /--* t13 long
  3650. Generating: N008 ( 5, 12) [000014] nc---------- t14 = * IND int REG NA
  3651. Generating: N010 ( 1, 1) [000015] -c---------- t15 = CNS_INT int 0 REG NA
  3652. /--* t14 int
  3653. +--* t15 int
  3654. Generating: N012 ( 7, 14) [000016] J------N---- * EQ void REG NA
  3655. IN0001: cmp dword ptr [(reloc 0x7fff4561eaf0)], 0
  3656. Generating: N014 ( 9, 16) [000022] ------------ * JTRUE void REG NA
  3657. IN0002: je L_M60652_BB04
  3658.  
  3659. Scope info: end block BB02, IL range [???..???)
  3660. Scope info: ignoring block end
  3661.  
  3662. =============== Generating BB03 [???..???), preds={BB02} succs={BB04} flags=0x00000000.40000040: internal LIR
  3663. BB03 IN (0)={} + ByrefExposed + GcHeap
  3664. OUT(0)={} + ByrefExposed + GcHeap
  3665.  
  3666. Liveness not changing: 0000000000000000 {}
  3667. Live regs: (unchanged) 00000000 {}
  3668. GC regs: (unchanged) 00000000 {}
  3669. Byref regs: (unchanged) 00000000 {}
  3670.  
  3671. L_M60652_BB03:
  3672.  
  3673. G_M60652_IG02: ; offs=000000H, funclet=00, bbWeight=1
  3674. Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  3675.  
  3676. Scope info: begin block BB03, IL range [???..???)
  3677. Scope info: ignoring block beginning
  3678. genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
  3679. Generating: N018 ( 14, 5) [000017] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  3680. Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  3681. IN0003: call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  3682.  
  3683. Scope info: end block BB03, IL range [???..???)
  3684. Scope info: ignoring block end
  3685.  
  3686. =============== Generating BB04 [???..???), preds={BB02,BB03} succs={BB05} flags=0x00000000.40030060: i internal label target LIR
  3687. BB04 IN (0)={} + ByrefExposed + GcHeap
  3688. OUT(0)={} + ByrefExposed + GcHeap
  3689.  
  3690. Liveness not changing: 0000000000000000 {}
  3691. Live regs: (unchanged) 00000000 {}
  3692. GC regs: (unchanged) 00000000 {}
  3693. Byref regs: (unchanged) 00000000 {}
  3694.  
  3695. L_M60652_BB04:
  3696.  
  3697. G_M60652_IG03: ; offs=00000DH, funclet=00, bbWeight=0.50
  3698. Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  3699.  
  3700. Scope info: begin block BB04, IL range [???..???)
  3701. Scope info: ignoring block beginning
  3702. genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
  3703.  
  3704. Scope info: end block BB04, IL range [???..???)
  3705. Scope info: ignoring block end
  3706.  
  3707. =============== Generating BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06} flags=0x00000000.40000020: i LIR
  3708. BB05 IN (0)={} + ByrefExposed + GcHeap
  3709. OUT(0)={} + ByrefExposed + GcHeap
  3710.  
  3711. Liveness not changing: 0000000000000000 {}
  3712. Live regs: (unchanged) 00000000 {}
  3713. GC regs: (unchanged) 00000000 {}
  3714. Byref regs: (unchanged) 00000000 {}
  3715.  
  3716. L_M60652_BB05:
  3717.  
  3718. Scope info: begin block BB05, IL range [000..00D)
  3719. Scope info: opening scope, LVnum=1 [000..00F)
  3720. Scope info: >> new scope, VarNum=1, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
  3721. Scope info: opening scope, LVnum=0 [000..00F)
  3722. Scope info: >> new scope, VarNum=0, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
  3723. Scope info: open scopes =
  3724. 1 (V01 loc1) [000..00F)
  3725. 0 (V00 loc0) [000..00F)
  3726. Added IP mapping: 0x0000 STACK_EMPTY (G_M60652_IG04,ins#0,ofs#0) label
  3727. Generating: N024 (???,???) [000023] ------------ IL_OFFSET void IL offset: 0x0 REG NA
  3728. Generating: N026 ( 1, 1) [000001] ------------ NO_OP void REG NA
  3729. IN0004: nop
  3730. Added IP mapping: 0x0001 STACK_EMPTY (G_M60652_IG04,ins#1,ofs#1)
  3731. Generating: N028 (???,???) [000024] ------------ IL_OFFSET void IL offset: 0x1 REG NA
  3732. Generating: N030 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 REG NA
  3733. /--* t4 int
  3734. Generating: N032 ( 2, 2) [000021] ------------ t21 = * SIMD simd16 double init REG mm0
  3735. IN0005: vxorps xmm0, xmm0
  3736. /--* t21 simd16
  3737. Generating: N034 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0 NA REG NA
  3738. IN0006: vmovapd xmmword ptr [V00 rbp-10H], xmm0
  3739. Added IP mapping: 0x0009 STACK_EMPTY (G_M60652_IG04,ins#3,ofs#12)
  3740. Generating: N036 (???,???) [000025] ------------ IL_OFFSET void IL offset: 0x9 REG NA
  3741. Generating: N038 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V00 loc0 mm0 REG mm0
  3742. IN0007: vmovapd xmm0, xmmword ptr [V00 rbp-10H]
  3743. /--* t6 simd16
  3744. Generating: N040 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1 NA REG NA
  3745. IN0008: vmovapd xmmword ptr [V01 rbp-20H], xmm0
  3746. Added IP mapping: 0x000B STACK_EMPTY (G_M60652_IG04,ins#5,ofs#24)
  3747. Generating: N042 (???,???) [000026] ------------ IL_OFFSET void IL offset: 0xb REG NA
  3748. Generating: N044 ( 0, 0) [000010] ------------ NOP void REG NA
  3749. IN0009: nop
  3750.  
  3751. Scope info: end block BB05, IL range [000..00D)
  3752. Scope info: open scopes =
  3753. 1 (V01 loc1) [000..00F)
  3754. 0 (V00 loc0) [000..00F)
  3755. IN000a: jmp L_M60652_BB06
  3756.  
  3757. =============== Generating BB06 [00D..00F) (return), preds={BB05} succs={} flags=0x00000000.40030020: i label target LIR
  3758. BB06 IN (0)={} + ByrefExposed + GcHeap
  3759. OUT(0)={} + ByrefExposed + GcHeap
  3760.  
  3761. Liveness not changing: 0000000000000000 {}
  3762. Live regs: (unchanged) 00000000 {}
  3763. GC regs: (unchanged) 00000000 {}
  3764. Byref regs: (unchanged) 00000000 {}
  3765.  
  3766. L_M60652_BB06:
  3767.  
  3768. G_M60652_IG04: ; offs=000012H, funclet=00, bbWeight=1
  3769. Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  3770.  
  3771. Scope info: begin block BB06, IL range [00D..00F)
  3772. Scope info: open scopes =
  3773. 1 (V01 loc1) [000..00F)
  3774. 0 (V00 loc0) [000..00F)
  3775. Added IP mapping: 0x000D STACK_EMPTY (G_M60652_IG05,ins#0,ofs#0) label
  3776. Generating: N048 (???,???) [000027] ------------ IL_OFFSET void IL offset: 0xd REG NA
  3777. Generating: N050 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc1 mm0 REG mm0
  3778. IN000b: vmovapd xmm0, xmmword ptr [V01 rbp-20H]
  3779. /--* t11 simd16
  3780. Generating: N052 ( 4, 3) [000012] ------------ * RETURN simd16 REG NA
  3781.  
  3782. Scope info: end block BB06, IL range [00D..00F)
  3783. Scope info: ending scope, LVnum=1 [000..00F)
  3784. Scope info: ending scope, LVnum=0 [000..00F)
  3785. Scope info: open scopes =
  3786. <none>
  3787. Added IP mapping: EPILOG STACK_EMPTY (G_M60652_IG05,ins#1,ofs#6) label
  3788. Reserving epilog IG for block BB06
  3789.  
  3790. G_M60652_IG05: ; offs=000030H, funclet=00, bbWeight=1
  3791. *************** After placeholder IG creation
  3792. G_M60652_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
  3793. G_M60652_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3794. G_M60652_IG03: ; offs=00000DH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3795. G_M60652_IG04: ; offs=000012H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3796. G_M60652_IG05: ; offs=000030H, size=0006H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3797. G_M60652_IG06: ; epilog placeholder, next placeholder=<END>, BB06 [0002], epilog, extend <-- First placeholder <-- Last placeholder
  3798. ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
  3799. ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
  3800. Liveness not changing: 0000000000000000 {}
  3801.  
  3802. # compCycleEstimate = 41, compSizeEstimate = 35 CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  3803. ; Final local variable assignments
  3804. ;
  3805. ; V00 loc0 [V00 ] ( 1, 1 ) simd16 -> [rbp-0x10] must-init ld-addr-op
  3806. ; V01 loc1 [V01 ] ( 1, 1 ) simd16 -> [rbp-0x20] must-init
  3807. ; V02 OutArgs [V02 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
  3808. ;
  3809. ; Lcl frame size = 64
  3810. *************** Before prolog / epilog generation
  3811. G_M60652_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
  3812. G_M60652_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3813. G_M60652_IG03: ; offs=00000DH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3814. G_M60652_IG04: ; offs=000012H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3815. G_M60652_IG05: ; offs=000030H, size=0006H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3816. G_M60652_IG06: ; epilog placeholder, next placeholder=<END>, BB06 [0002], epilog, extend <-- First placeholder <-- Last placeholder
  3817. ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
  3818. ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
  3819. *************** In genFnProlog()
  3820. Added IP mapping to front: PROLOG STACK_EMPTY (G_M60652_IG01,ins#0,ofs#0) label
  3821.  
  3822. __prolog:
  3823. Found 8 lvMustInit int-sized stack slots, frame offsets 32 through 0
  3824. IN000c: push rbp
  3825. IN000d: sub rsp, 64
  3826. IN000e: vzeroupper
  3827. IN000f: lea rbp, [rsp+40H]
  3828. IN0010: xor rax, rax
  3829. IN0011: mov qword ptr [V00 rbp-10H], rax
  3830. IN0012: mov qword ptr [V00+0x8 rbp-08H], rax
  3831. IN0013: mov qword ptr [V01 rbp-20H], rax
  3832. IN0014: mov qword ptr [V01+0x8 rbp-18H], rax
  3833. *************** In genEnregisterIncomingStackArgs()
  3834.  
  3835.  
  3836. G_M60652_IG01: ; offs=000000H, funclet=00, bbWeight=1
  3837. *************** In genFnEpilog()
  3838.  
  3839. __epilog:
  3840. gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
  3841. IN0015: lea rsp, [rbp]
  3842. IN0016: pop rbp
  3843. IN0017: ret
  3844.  
  3845. G_M60652_IG06: ; offs=000036H, funclet=00, bbWeight=1
  3846. 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
  3847. *************** After prolog / epilog generation
  3848. G_M60652_IG01: ; func=00, offs=000000H, size=001FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  3849. G_M60652_IG02: ; offs=00001FH, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3850. G_M60652_IG03: ; offs=00002CH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3851. G_M60652_IG04: ; offs=000031H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3852. G_M60652_IG05: ; offs=00004FH, size=0006H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3853. G_M60652_IG06: ; offs=000055H, size=0006H, epilog, nogc, extend
  3854. *************** In emitJumpDistBind()
  3855. Binding: IN0002: 000000 je L_M60652_BB04
  3856. Binding L_M60652_BB04to G_M60652_IG04
  3857. Estimate of fwd jump [647DD4B4/002]: 0026 -> 0031 = 0009
  3858. Shrinking jump [647DD4B4/002]
  3859. Adjusted offset of BB03 from 002C to 0028
  3860. Adjusted offset of BB04 from 0031 to 002D
  3861. Binding: IN000a: 000000 jmp L_M60652_BB06
  3862. Binding L_M60652_BB06to G_M60652_IG05
  3863. Estimate of fwd jump [647DD96C/010]: 0046 -> 004B = 0003
  3864. Shrinking jump [647DD96C/010]
  3865. Adjusted offset of BB05 from 004F to 0048
  3866. Adjusted offset of BB06 from 0055 to 004E
  3867. Total shrinkage = 7, min extra jump size = 4294967295
  3868.  
  3869. Hot code size = 0x54 bytes
  3870. Cold code size = 0x0 bytes
  3871. reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x8)
  3872. *************** In emitEndCodeGen()
  3873. Converting emitMaxStackDepth from bytes (0) to elements (0)
  3874.  
  3875. ***************************************************************************
  3876. Instructions as they come out of the scheduler
  3877.  
  3878.  
  3879. G_M60652_IG01: ; func=00, offs=000000H, size=001FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  3880. IN000c: 000000 55 push rbp
  3881. IN000d: 000001 4883EC40 sub rsp, 64
  3882. IN000e: 000005 C5F877 vzeroupper
  3883. IN000f: 000008 488D6C2440 lea rbp, [rsp+40H]
  3884. IN0010: 00000D 33C0 xor rax, rax
  3885. IN0011: 00000F 488945F0 mov qword ptr [rbp-10H], rax
  3886. IN0012: 000013 488945F8 mov qword ptr [rbp-08H], rax
  3887. IN0013: 000017 488945E0 mov qword ptr [rbp-20H], rax
  3888. IN0014: 00001B 488945E8 mov qword ptr [rbp-18H], rax
  3889. ;; bbWeight=1 PerfScore 7.00
  3890. G_M60652_IG02: ; func=00, offs=00001FH, size=0009H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  3891. IN0001: 00001F 833D7A6D1F0000 cmp dword ptr [(reloc 0x7fff4561eaf0)], 0
  3892. IN0002: 000026 7405 je SHORT G_M60652_IG04
  3893. ;; bbWeight=1 PerfScore 3.00
  3894. G_M60652_IG03: ; func=00, offs=000028H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3895. [647DDF10] ptr arg pop 0
  3896. IN0003: 000028 E8C3B2A15E call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  3897. ;; bbWeight=0.50 PerfScore 0.50
  3898. G_M60652_IG04: ; func=00, offs=00002DH, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  3899. IN0004: 00002D 90 nop
  3900. IN0005: 00002E C5F857C0 vxorps xmm0, xmm0 (ECS:5, ACS:4)
  3901. Instruction predicted size = 5, actual = 4
  3902. IN0006: 000032 C5F92945F0 vmovapd xmmword ptr [rbp-10H], xmm0 (ECS:6, ACS:5)
  3903. Instruction predicted size = 6, actual = 5
  3904. IN0007: 000037 C5F92845F0 vmovapd xmm0, xmmword ptr [rbp-10H] (ECS:6, ACS:5)
  3905. Instruction predicted size = 6, actual = 5
  3906. IN0008: 00003C C5F92945E0 vmovapd xmmword ptr [rbp-20H], xmm0 (ECS:6, ACS:5)
  3907. Instruction predicted size = 6, actual = 5
  3908. IN0009: 000041 90 nop
  3909. IN000a: 000042 EB04 jmp SHORT G_M60652_IG05
  3910. ;; bbWeight=1 PerfScore 9.83
  3911. G_M60652_IG05: ; func=00, offs=000048H, size=0006H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3912. Block predicted offs = 00000048, actual = 00000044 -> size adj = 4
  3913. IN000b: 000044 C5F92845E0 vmovapd xmm0, xmmword ptr [rbp-20H] (ECS:6, ACS:5)
  3914. Instruction predicted size = 6, actual = 5
  3915. ;; bbWeight=1 PerfScore 3.00
  3916. G_M60652_IG06: ; func=00, offs=00004EH, size=0006H, epilog, nogc, extend
  3917. Block predicted offs = 0000004E, actual = 00000049 -> size adj = 5
  3918. IN0015: 000049 488D6500 lea rsp, [rbp]
  3919. IN0016: 00004D 5D pop rbp
  3920. IN0017: 00004E C3 ret
  3921. ;; bbWeight=1 PerfScore 2.00Allocated method code size = 84 , actual size = 79
  3922.  
  3923. ; Total bytes of code 79, prolog size 31, PerfScore 33.73, (MethodHash=f5b01313) for method CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  3924. ; ============================================================
  3925.  
  3926. *************** After end code gen, before unwindEmit()
  3927. G_M60652_IG01: ; func=00, offs=000000H, size=001FH, bbWeight=1 PerfScore 7.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  3928.  
  3929. IN000c: 000000 push rbp
  3930. IN000d: 000001 sub rsp, 64
  3931. IN000e: 000005 vzeroupper
  3932. IN000f: 000008 lea rbp, [rsp+40H]
  3933. IN0010: 00000D xor rax, rax
  3934. IN0011: 00000F mov qword ptr [V00 rbp-10H], rax
  3935. IN0012: 000013 mov qword ptr [V00+0x8 rbp-08H], rax
  3936. IN0013: 000017 mov qword ptr [V01 rbp-20H], rax
  3937. IN0014: 00001B mov qword ptr [V01+0x8 rbp-18H], rax
  3938.  
  3939. G_M60652_IG02: ; offs=00001FH, size=0009H, bbWeight=1 PerfScore 3.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  3940.  
  3941. IN0001: 00001F cmp dword ptr [(reloc 0x7fff4561eaf0)], 0
  3942. IN0002: 000026 je SHORT G_M60652_IG04
  3943.  
  3944. G_M60652_IG03: ; offs=000028H, size=0005H, bbWeight=0.50 PerfScore 0.50, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  3945.  
  3946. IN0003: 000028 call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  3947.  
  3948. G_M60652_IG04: ; offs=00002DH, size=0017H, bbWeight=1 PerfScore 9.83, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  3949.  
  3950. IN0004: 00002D nop
  3951. IN0005: 00002E vxorps xmm0, xmm0
  3952. IN0006: 000032 vmovapd xmmword ptr [V00 rbp-10H], xmm0
  3953. IN0007: 000037 vmovapd xmm0, xmmword ptr [V00 rbp-10H]
  3954. IN0008: 00003C vmovapd xmmword ptr [V01 rbp-20H], xmm0
  3955. IN0009: 000041 nop
  3956. IN000a: 000042 jmp SHORT G_M60652_IG05
  3957.  
  3958. G_M60652_IG05: ; offs=000044H, size=0005H, bbWeight=1 PerfScore 3.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  3959.  
  3960. IN000b: 000044 vmovapd xmm0, xmmword ptr [V01 rbp-20H]
  3961.  
  3962. G_M60652_IG06: ; offs=000049H, size=0006H, bbWeight=1 PerfScore 2.00, epilog, nogc, extend
  3963.  
  3964. IN0015: 000049 lea rsp, [rbp]
  3965. IN0016: 00004D pop rbp
  3966. IN0017: 00004E ret
  3967.  
  3968. Unwind Info:
  3969. >> Start offset : 0x000000 (not in unwind data)
  3970. >> End offset : 0x00004f (not in unwind data)
  3971. Version : 1
  3972. Flags : 0x00
  3973. SizeOfProlog : 0x05
  3974. CountOfUnwindCodes: 2
  3975. FrameRegister : none (0)
  3976. FrameOffset : N/A (no FrameRegister) (Value=0)
  3977. UnwindCodes :
  3978. CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 7 * 8 + 8 = 64 = 0x40
  3979. CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
  3980. allocUnwindInfo(pHotCode=0x00007FFF45427D50, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x4f, unwindSize=0x8, pUnwindBlock=0x000001A2647DACD0, funKind=0 (main function))
  3981. *************** In genIPmappingGen()
  3982. IP mapping count : 8
  3983. IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
  3984. IL offs NO_MAP : 0x0000001F ( STACK_EMPTY )
  3985. IL offs 0x0000 : 0x0000002D ( STACK_EMPTY )
  3986. IL offs 0x0001 : 0x0000002E ( STACK_EMPTY )
  3987. IL offs 0x0009 : 0x00000037 ( STACK_EMPTY )
  3988. IL offs 0x000B : 0x00000041 ( STACK_EMPTY )
  3989. IL offs 0x000D : 0x00000044 ( STACK_EMPTY )
  3990. IL offs EPILOG : 0x00000049 ( STACK_EMPTY )
  3991.  
  3992. *************** In genSetScopeInfo()
  3993. VarLocInfo count is 2
  3994. *************** Variable debug info
  3995. 2 live ranges
  3996. 1( UNKNOWN) : From 0000002Dh to 00000049h, in rbp[-32] (1 slot)
  3997. 0( UNKNOWN) : From 0000002Dh to 00000049h, in rbp[-16] (1 slot)
  3998. *************** In gcInfoBlockHdrSave()
  3999. Set code length to 79.
  4000. Set ReturnKind to Scalar.
  4001. Set stack base register to rbp.
  4002. Set Outgoing stack arg area size to 32.
  4003. Defining interruptible range: [0x1f, 0x49).
  4004. Method code size: 79
  4005.  
  4006. Allocations for CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double] (MethodHash=f5b01313)
  4007. count: 284, size: 27929, max = 2640
  4008. allocateMemory: 65536, nraUsed: 30360
  4009.  
  4010. Alloc'd bytes by kind:
  4011. kind | size | pct
  4012. ---------------------+------------+--------
  4013. AssertionProp | 0 | 0.00%
  4014. ASTNode | 3784 | 13.55%
  4015. InstDesc | 3620 | 12.96%
  4016. ImpStack | 384 | 1.37%
  4017. BasicBlock | 2224 | 7.96%
  4018. fgArgInfo | 0 | 0.00%
  4019. fgArgInfoPtrArr | 0 | 0.00%
  4020. FlowList | 192 | 0.69%
  4021. TreeStatementList | 0 | 0.00%
  4022. SiScope | 128 | 0.46%
  4023. DominatorMemory | 0 | 0.00%
  4024. LSRA | 3260 | 11.67%
  4025. LSRA_Interval | 264 | 0.95%
  4026. LSRA_RefPosition | 1664 | 5.96%
  4027. Reachability | 0 | 0.00%
  4028. SSA | 0 | 0.00%
  4029. ValueNumber | 0 | 0.00%
  4030. LvaTable | 1920 | 6.87%
  4031. UnwindInfo | 0 | 0.00%
  4032. hashBv | 120 | 0.43%
  4033. bitset | 56 | 0.20%
  4034. FixedBitVect | 8 | 0.03%
  4035. Generic | 1218 | 4.36%
  4036. LocalAddressVisitor | 0 | 0.00%
  4037. FieldSeqStore | 0 | 0.00%
  4038. ZeroOffsetFieldMap | 40 | 0.14%
  4039. ArrayInfoMap | 0 | 0.00%
  4040. MemoryPhiArg | 0 | 0.00%
  4041. CSE | 0 | 0.00%
  4042. GC | 1360 | 4.87%
  4043. CorSig | 0 | 0.00%
  4044. Inlining | 120 | 0.43%
  4045. ArrayStack | 0 | 0.00%
  4046. DebugInfo | 336 | 1.20%
  4047. DebugOnly | 5925 | 21.21%
  4048. Codegen | 1128 | 4.04%
  4049. LoopOpt | 0 | 0.00%
  4050. LoopHoist | 0 | 0.00%
  4051. Unknown | 106 | 0.38%
  4052. RangeCheck | 0 | 0.00%
  4053. CopyProp | 0 | 0.00%
  4054. SideEffects | 0 | 0.00%
  4055. ObjectAllocator | 0 | 0.00%
  4056. VariableLiveRanges | 0 | 0.00%
  4057. ClassLayout | 72 | 0.26%
  4058. TailMergeThrows | 0 | 0.00%
  4059.  
  4060. ****** DONE compiling CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
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