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  1. Index: rtl8169.c
  2. ===================================================================
  3. RCS file: /cvsroot/src/sys/dev/ic/rtl8169.c,v
  4. retrieving revision 1.133
  5. diff -u -r1.133 rtl8169.c
  6. --- rtl8169.c 28 Jul 2010 23:30:21 -0000 1.133
  7. +++ rtl8169.c 19 Sep 2011 18:53:39 -0000
  8. @@ -110,7 +110,10 @@
  9. * jumbo frames larger than 7.5K, so the max MTU possible with this
  10. * driver is 7500 bytes.
  11. */
  12. -
  13. +/*
  14. + * Support for timer interrupts isn't implemented in (most versions of) QEMU!!!
  15. + */
  16. +#define RTK_QEMU
  17.  
  18. #include <sys/param.h>
  19. #include <sys/endian.h>
  20. @@ -1365,7 +1368,9 @@
  21. * This is done in case the transmitter has gone idle.
  22. */
  23. if (sc->re_ldata.re_txq_free < RE_TX_QLEN) {
  24. +#ifndef RTK_QEMU
  25. CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
  26. +#endif
  27. if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
  28. /*
  29. * Some chips will ignore a second TX request
  30. @@ -1430,8 +1435,13 @@
  31. if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR))
  32. re_rxeof(sc);
  33.  
  34. - if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR |
  35. - RTK_ISR_TX_DESC_UNAVAIL))
  36. + if (status & (
  37. +#ifdef RTK_QEMU
  38. + RTK_ISR_TX_OK |
  39. +#else
  40. + RTK_ISR_TIMEOUT_EXPIRED |
  41. +#endif
  42. + RTK_ISR_TX_ERR | RTK_ISR_TX_DESC_UNAVAIL))
  43. re_txeof(sc);
  44.  
  45. if (status & RTK_ISR_SYSTEM_ERR) {
  46. @@ -1691,6 +1701,7 @@
  47. else
  48. CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
  49.  
  50. +#ifndef RTK_QEMU
  51. /*
  52. * Use the countdown timer for interrupt moderation.
  53. * 'TX done' interrupts are disabled. Instead, we reset the
  54. @@ -1700,6 +1711,7 @@
  55. * the timer count is reset to 0.
  56. */
  57. CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
  58. +#endif
  59.  
  60. /*
  61. * Set a timeout in case the chip goes out to lunch.
  62. @@ -1853,6 +1865,7 @@
  63. CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
  64. #endif
  65.  
  66. +#ifndef RTK_QEMU
  67. /*
  68. * Initialize the timer interrupt register so that
  69. * a timer interrupt will be generated once the timer
  70. @@ -1865,6 +1878,9 @@
  71. CSR_WRITE_4(sc, RTK_TIMERINT, 0x400);
  72. else {
  73. CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800);
  74. +#else
  75. + if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
  76. +#endif
  77.  
  78. /*
  79. * For 8169 gigE NICs, set the max allowed RX packet
  80. Index: rtl81x9reg.h
  81. ===================================================================
  82. RCS file: /cvsroot/src/sys/dev/ic/rtl81x9reg.h,v
  83. retrieving revision 1.41
  84. diff -u -r1.41 rtl81x9reg.h
  85. --- rtl81x9reg.h 9 Apr 2010 10:40:59 -0000 1.41
  86. +++ rtl81x9reg.h 19 Sep 2011 18:53:39 -0000
  87. @@ -232,11 +232,17 @@
  88. (RTK_ISR_TX_OK|RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR| \
  89. RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \
  90. RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR)
  91. -
  92. +#ifdef RTK_QEMU
  93. +#define RTK_INTRS_CPLUS \
  94. + (RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR|RTK_ISR_TX_OK| \
  95. + RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \
  96. + RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR|RTK_ISR_TIMEOUT_EXPIRED)
  97. +#else
  98. #define RTK_INTRS_CPLUS \
  99. (RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR| \
  100. RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \
  101. RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR|RTK_ISR_TIMEOUT_EXPIRED)
  102. +#endif
  103.  
  104.  
  105. /*
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