Clock Divider

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ClockDivider is
    Port ( CLK_IN : in  STD_LOGIC;
           RESET : in  STD_LOGIC;
           CLK_OUT : out  STD_LOGIC);
end ClockDivider;

architecture Behavioral of ClockDivider is

begin

    ClockDividerProcess:process(CLK_IN, RESET)
        variable counter : integer range 0 to 50000000 := 0;
        variable clk_out_var : std_logic := '0';
    begina
        if(RESET = '1') then
            counter := 0;
            clk_out_var := '0';
        elsif(CLK_IN' event and CLK_IN = '0') then
            counter := counter + 1;
            if(counter = 25000000) then -- toggle each 25M clocks, divides by 50M (becomes 1 Hz)
                counter := 0;
                clk_out_var := not clk_out_var;
            else
                clk_out_var := clk_out_var;
            end if;
        end if;
        CLK_OUT <= clk_out_var;
    end process;

end Behavioral;