API tools faq
paste
Advertisement
Guest User

clearfog.dts

a guest
Mar 29th, 2022
23
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 26.30 KB | None | 0 0
raw download clone embed print report
  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = < 0x01 >;
  5. #size-cells = < 0x01 >;
  6. model = "SolidRun Clearfog A1";
  7. compatible = "solidrun,clearfog-a1\0marvell,armada388\0marvell,armada385\0marvell,armada380";
  8.  
  9. aliases {
  10. gpio0 = "/soc/internal-regs/gpio@18100";
  11. gpio1 = "/soc/internal-regs/gpio@18140";
  12. serial0 = "/soc/internal-regs/serial@12000";
  13. serial1 = "/soc/internal-regs/serial@12100";
  14. ethernet1 = "/soc/internal-regs/ethernet@70000";
  15. ethernet2 = "/soc/internal-regs/ethernet@30000";
  16. ethernet3 = "/soc/internal-regs/ethernet@34000";
  17. };
  18.  
  19. pmu {
  20. compatible = "arm,cortex-a9-pmu";
  21. interrupts-extended = < 0x01 0x03 >;
  22. };
  23.  
  24. soc {
  25. compatible = "marvell,armada380-mbus\0simple-bus";
  26. #address-cells = < 0x02 >;
  27. #size-cells = < 0x01 >;
  28. controller = < 0x02 >;
  29. interrupt-parent = < 0x03 >;
  30. pcie-mem-aperture = < 0xe0000000 0x8000000 >;
  31. pcie-io-aperture = < 0xe8000000 0x100000 >;
  32. ranges = < 0xf0010000 0x00 0xf1000000 0x100000 0x11d0000 0x00 0xfff00000 0x100000 0x9190000 0x00 0xf1100000 0x10000 0x9150000 0x00 0xf1110000 0x10000 0xc040000 0x00 0xf1200000 0x100000 >;
  33.  
  34. bootrom {
  35. compatible = "marvell,bootrom";
  36. reg = < 0x11d0000 0x00 0x200000 >;
  37. };
  38.  
  39. devbus-bootcs {
  40. compatible = "marvell,mvebu-devbus";
  41. reg = < 0xf0010000 0x10400 0x08 >;
  42. ranges = < 0x00 0x12f0000 0x00 0xffffffff >;
  43. #address-cells = < 0x01 >;
  44. #size-cells = < 0x01 >;
  45. clocks = < 0x04 0x00 >;
  46. status = "disabled";
  47. };
  48.  
  49. devbus-cs0 {
  50. compatible = "marvell,mvebu-devbus";
  51. reg = < 0xf0010000 0x10408 0x08 >;
  52. ranges = < 0x00 0x13e0000 0x00 0xffffffff >;
  53. #address-cells = < 0x01 >;
  54. #size-cells = < 0x01 >;
  55. clocks = < 0x04 0x00 >;
  56. status = "disabled";
  57. };
  58.  
  59. devbus-cs1 {
  60. compatible = "marvell,mvebu-devbus";
  61. reg = < 0xf0010000 0x10410 0x08 >;
  62. ranges = < 0x00 0x13d0000 0x00 0xffffffff >;
  63. #address-cells = < 0x01 >;
  64. #size-cells = < 0x01 >;
  65. clocks = < 0x04 0x00 >;
  66. status = "disabled";
  67. };
  68.  
  69. devbus-cs2 {
  70. compatible = "marvell,mvebu-devbus";
  71. reg = < 0xf0010000 0x10418 0x08 >;
  72. ranges = < 0x00 0x13b0000 0x00 0xffffffff >;
  73. #address-cells = < 0x01 >;
  74. #size-cells = < 0x01 >;
  75. clocks = < 0x04 0x00 >;
  76. status = "disabled";
  77. };
  78.  
  79. devbus-cs3 {
  80. compatible = "marvell,mvebu-devbus";
  81. reg = < 0xf0010000 0x10420 0x08 >;
  82. ranges = < 0x00 0x1370000 0x00 0xffffffff >;
  83. #address-cells = < 0x01 >;
  84. #size-cells = < 0x01 >;
  85. clocks = < 0x04 0x00 >;
  86. status = "disabled";
  87. };
  88.  
  89. internal-regs {
  90. compatible = "simple-bus";
  91. #address-cells = < 0x01 >;
  92. #size-cells = < 0x01 >;
  93. ranges = < 0x00 0xf0010000 0x00 0x100000 >;
  94.  
  95. sdramc@1400 {
  96. compatible = "marvell,armada-xp-sdram-controller";
  97. reg = < 0x1400 0x500 >;
  98. };
  99.  
  100. cache-controller@8000 {
  101. compatible = "arm,pl310-cache";
  102. reg = < 0x8000 0x1000 >;
  103. cache-unified;
  104. cache-level = < 0x02 >;
  105. arm,double-linefill-incr = < 0x00 >;
  106. arm,double-linefill-wrap = < 0x00 >;
  107. arm,double-linefill = < 0x00 >;
  108. prefetch-data = < 0x01 >;
  109. };
  110.  
  111. scu@c000 {
  112. compatible = "arm,cortex-a9-scu";
  113. reg = < 0xc000 0x58 >;
  114. };
  115.  
  116. timer@c200 {
  117. compatible = "arm,cortex-a9-global-timer";
  118. reg = < 0xc200 0x20 >;
  119. interrupts = < 0x01 0x0b 0x301 >;
  120. clocks = < 0x04 0x02 >;
  121. };
  122.  
  123. timer@c600 {
  124. compatible = "arm,cortex-a9-twd-timer";
  125. reg = < 0xc600 0x20 >;
  126. interrupts = < 0x01 0x0d 0x301 >;
  127. clocks = < 0x04 0x02 >;
  128. };
  129.  
  130. interrupt-controller@d000 {
  131. compatible = "arm,cortex-a9-gic";
  132. #interrupt-cells = < 0x03 >;
  133. #size-cells = < 0x00 >;
  134. interrupt-controller;
  135. reg = < 0xd000 0x1000 0xc100 0x100 >;
  136. phandle = < 0x03 >;
  137. };
  138.  
  139. i2c@11000 {
  140. compatible = "marvell,mv78230-a0-i2c\0marvell,mv64xxx-i2c";
  141. reg = < 0x11000 0x20 >;
  142. #address-cells = < 0x01 >;
  143. #size-cells = < 0x00 >;
  144. interrupts = < 0x00 0x02 0x04 >;
  145. clocks = < 0x04 0x00 >;
  146. status = "okay";
  147. clock-frequency = < 0x61a80 >;
  148. pinctrl-0 = < 0x05 >;
  149. pinctrl-names = "default";
  150.  
  151. eeprom@53 {
  152. compatible = "atmel,24c02";
  153. reg = < 0x53 >;
  154. pagesize = < 0x10 >;
  155. };
  156.  
  157. gpio-expander@20 {
  158. compatible = "nxp,pca9555";
  159. gpio-controller;
  160. #gpio-cells = < 0x02 >;
  161. reg = < 0x20 >;
  162. phandle = < 0x22 >;
  163.  
  164. pcie1-0-clkreq-hog {
  165. gpio-hog;
  166. gpios = < 0x00 0x01 >;
  167. input;
  168. line-name = "pcie1.0-clkreq";
  169. };
  170.  
  171. pcie1-0-w-disable-hog {
  172. gpio-hog;
  173. gpios = < 0x03 0x01 >;
  174. output-low;
  175. line-name = "pcie1.0-w-disable";
  176. };
  177.  
  178. usb3-ilimit-hog {
  179. gpio-hog;
  180. gpios = < 0x05 0x01 >;
  181. input;
  182. line-name = "usb3-current-limit";
  183. };
  184.  
  185. usb3-power-hog {
  186. gpio-hog;
  187. gpios = < 0x06 0x00 >;
  188. output-high;
  189. line-name = "usb3-power";
  190. };
  191.  
  192. m2-devslp-hog {
  193. gpio-hog;
  194. gpios = < 0x0b 0x00 >;
  195. output-low;
  196. line-name = "m.2 devslp";
  197. };
  198.  
  199. pcie2-0-clkreq-hog {
  200. gpio-hog;
  201. gpios = < 0x04 0x01 >;
  202. input;
  203. line-name = "pcie2.0-clkreq";
  204. };
  205.  
  206. pcie2-0-w-disable-hog {
  207. gpio-hog;
  208. gpios = < 0x07 0x01 >;
  209. output-low;
  210. line-name = "pcie2.0-w-disable";
  211. };
  212. };
  213.  
  214. mcp3021@4c {
  215. compatible = "microchip,mcp3021";
  216. reg = < 0x4c >;
  217. };
  218.  
  219. eeprom@52 {
  220. compatible = "atmel,24c02";
  221. reg = < 0x52 >;
  222. pagesize = < 0x10 >;
  223. };
  224. };
  225.  
  226. i2c@11100 {
  227. compatible = "marvell,mv78230-a0-i2c\0marvell,mv64xxx-i2c";
  228. reg = < 0x11100 0x20 >;
  229. #address-cells = < 0x01 >;
  230. #size-cells = < 0x00 >;
  231. interrupts = < 0x00 0x03 0x04 >;
  232. clocks = < 0x04 0x00 >;
  233. status = "okay";
  234. clock-frequency = < 0x186a0 >;
  235. pinctrl-0 = < 0x06 >;
  236. pinctrl-names = "default";
  237. phandle = < 0x23 >;
  238. };
  239.  
  240. serial@12000 {
  241. compatible = "marvell,armada-38x-uart\0ns16550a";
  242. reg = < 0x12000 0x100 >;
  243. reg-shift = < 0x02 >;
  244. interrupts = < 0x00 0x0c 0x04 >;
  245. reg-io-width = < 0x01 >;
  246. clocks = < 0x04 0x00 >;
  247. status = "okay";
  248. pinctrl-0 = < 0x07 >;
  249. pinctrl-names = "default";
  250. };
  251.  
  252. serial@12100 {
  253. compatible = "marvell,armada-38x-uart\0ns16550a";
  254. reg = < 0x12100 0x100 >;
  255. reg-shift = < 0x02 >;
  256. interrupts = < 0x00 0x0d 0x04 >;
  257. reg-io-width = < 0x01 >;
  258. clocks = < 0x04 0x00 >;
  259. status = "okay";
  260. pinctrl-0 = < 0x08 >;
  261. pinctrl-names = "default";
  262. };
  263.  
  264. pinctrl@18000 {
  265. reg = < 0x18000 0x20 >;
  266. compatible = "marvell,mv88f6828-pinctrl";
  267.  
  268. ge-rgmii-pins-0 {
  269. marvell,pins = "mpp6\0mpp7\0mpp8\0mpp9\0mpp10\0mpp11\0mpp12\0mpp13\0mpp14\0mpp15\0mpp16\0mpp17";
  270. marvell,function = "ge0";
  271. phandle = < 0x0b >;
  272. };
  273.  
  274. ge-rgmii-pins-1 {
  275. marvell,pins = "mpp21\0mpp27\0mpp28\0mpp29\0mpp30\0mpp31\0mpp32\0mpp37\0mpp38\0mpp39\0mpp40\0mpp41";
  276. marvell,function = "ge1";
  277. };
  278.  
  279. i2c-pins-0 {
  280. marvell,pins = "mpp2\0mpp3";
  281. marvell,function = "i2c0";
  282. phandle = < 0x05 >;
  283. };
  284.  
  285. mdio-pins {
  286. marvell,pins = "mpp4\0mpp5";
  287. marvell,function = "ge";
  288. phandle = < 0x11 >;
  289. };
  290.  
  291. ref-clk-pins-0 {
  292. marvell,pins = "mpp45";
  293. marvell,function = "ref";
  294. };
  295.  
  296. ref-clk-pins-1 {
  297. marvell,pins = "mpp46";
  298. marvell,function = "ref";
  299. };
  300.  
  301. spi-pins-0 {
  302. marvell,pins = "mpp22\0mpp23\0mpp24\0mpp25";
  303. marvell,function = "spi0";
  304. };
  305.  
  306. spi-pins-1 {
  307. marvell,pins = "mpp56\0mpp57\0mpp58\0mpp59";
  308. marvell,function = "spi1";
  309. phandle = < 0x1f >;
  310. };
  311.  
  312. nand-pins {
  313. marvell,pins = "mpp22\0mpp34\0mpp23\0mpp33\0mpp38\0mpp28\0mpp40\0mpp42\0mpp35\0mpp36\0mpp25\0mpp30\0mpp32";
  314. marvell,function = "dev";
  315. };
  316.  
  317. nand-rb {
  318. marvell,pins = "mpp41";
  319. marvell,function = "nand";
  320. };
  321.  
  322. uart-pins-0 {
  323. marvell,pins = "mpp0\0mpp1";
  324. marvell,function = "ua0";
  325. phandle = < 0x07 >;
  326. };
  327.  
  328. uart-pins-1 {
  329. marvell,pins = "mpp19\0mpp20";
  330. marvell,function = "ua1";
  331. };
  332.  
  333. sdhci-pins {
  334. marvell,pins = "mpp48\0mpp49\0mpp50\0mpp52\0mpp53\0mpp54\0mpp55\0mpp57\0mpp58\0mpp59";
  335. marvell,function = "sd0";
  336. };
  337.  
  338. sata-pins-0 {
  339. marvell,pins = "mpp20";
  340. marvell,function = "sata0";
  341. };
  342.  
  343. sata-pins-1 {
  344. marvell,pins = "mpp19";
  345. marvell,function = "sata1";
  346. };
  347.  
  348. sata-pins-2 {
  349. marvell,pins = "mpp47";
  350. marvell,function = "sata2";
  351. };
  352.  
  353. sata-pins-3 {
  354. marvell,pins = "mpp44";
  355. marvell,function = "sata3";
  356. };
  357.  
  358. microsom-phy-clk-pins {
  359. marvell,pins = "mpp45";
  360. marvell,function = "ref";
  361. phandle = < 0x12 >;
  362. };
  363.  
  364. microsom-sdhci-pins {
  365. marvell,pins = "mpp21\0mpp28\0mpp37\0mpp38\0mpp39\0mpp40";
  366. marvell,function = "sd0";
  367. phandle = < 0x1c >;
  368. };
  369.  
  370. i2c1-pins {
  371. marvell,pins = "mpp26\0mpp27";
  372. marvell,function = "i2c1";
  373. phandle = < 0x06 >;
  374. };
  375.  
  376. clearfog-sdhci-cd-pins {
  377. marvell,pins = "mpp20";
  378. marvell,function = "gpio";
  379. phandle = < 0x1d >;
  380. };
  381.  
  382. mikro-pins {
  383. marvell,pins = "mpp22\0mpp29";
  384. marvell,function = "gpio";
  385. };
  386.  
  387. mikro-spi-pins {
  388. marvell,pins = "mpp43";
  389. marvell,function = "spi1";
  390. phandle = < 0x21 >;
  391. };
  392.  
  393. mikro-uart-pins {
  394. marvell,pins = "mpp24\0mpp25";
  395. marvell,function = "ua1";
  396. phandle = < 0x08 >;
  397. };
  398.  
  399. clearfog-dsa0-clk-pins {
  400. marvell,pins = "mpp46";
  401. marvell,function = "ref";
  402. phandle = < 0x13 >;
  403. };
  404.  
  405. clearfog-dsa0-pins {
  406. marvell,pins = "mpp23\0mpp41";
  407. marvell,function = "gpio";
  408. phandle = < 0x14 >;
  409. };
  410.  
  411. spi1-cs-pins {
  412. marvell,pins = "mpp55";
  413. marvell,function = "spi1";
  414. phandle = < 0x20 >;
  415. };
  416.  
  417. rear-button-pins {
  418. marvell,pins = "mpp34";
  419. marvell,function = "gpio";
  420. phandle = < 0x24 >;
  421. };
  422. };
  423.  
  424. gpio@18100 {
  425. compatible = "marvell,armada-370-gpio\0marvell,orion-gpio";
  426. reg = < 0x18100 0x40 0x181c0 0x08 >;
  427. reg-names = "gpio\0pwm";
  428. ngpios = < 0x20 >;
  429. gpio-controller;
  430. #gpio-cells = < 0x02 >;
  431. #pwm-cells = < 0x02 >;
  432. interrupt-controller;
  433. #interrupt-cells = < 0x02 >;
  434. interrupts = < 0x00 0x35 0x04 0x00 0x36 0x04 0x00 0x37 0x04 0x00 0x38 0x04 >;
  435. clocks = < 0x04 0x00 >;
  436. phandle = < 0x1b >;
  437. };
  438.  
  439. gpio@18140 {
  440. compatible = "marvell,armada-370-gpio\0marvell,orion-gpio";
  441. reg = < 0x18140 0x40 0x181c8 0x08 >;
  442. reg-names = "gpio\0pwm";
  443. ngpios = < 0x1c >;
  444. gpio-controller;
  445. #gpio-cells = < 0x02 >;
  446. #pwm-cells = < 0x02 >;
  447. interrupt-controller;
  448. #interrupt-cells = < 0x02 >;
  449. interrupts = < 0x00 0x3a 0x04 0x00 0x3b 0x04 0x00 0x3c 0x04 0x00 0x3d 0x04 >;
  450. clocks = < 0x04 0x00 >;
  451. phandle = < 0x25 >;
  452. };
  453.  
  454. system-controller@18200 {
  455. compatible = "marvell,armada-380-system-controller\0marvell,armada-370-xp-system-controller";
  456. reg = < 0x18200 0x100 >;
  457. };
  458.  
  459. clock-gating-control@18220 {
  460. compatible = "marvell,armada-380-gating-clock";
  461. reg = < 0x18220 0x04 >;
  462. clocks = < 0x04 0x00 >;
  463. #clock-cells = < 0x01 >;
  464. phandle = < 0x0a >;
  465. };
  466.  
  467. phy@18300 {
  468. compatible = "marvell,armada-380-comphy";
  469. reg-names = "comphy\0conf";
  470. reg = < 0x18300 0x100 0x18460 0x04 >;
  471. #address-cells = < 0x01 >;
  472. #size-cells = < 0x00 >;
  473.  
  474. phy@0 {
  475. reg = < 0x00 >;
  476. #phy-cells = < 0x01 >;
  477. };
  478.  
  479. phy@1 {
  480. reg = < 0x01 >;
  481. #phy-cells = < 0x01 >;
  482. phandle = < 0x0e >;
  483. };
  484.  
  485. phy@2 {
  486. reg = < 0x02 >;
  487. #phy-cells = < 0x01 >;
  488. };
  489.  
  490. phy@3 {
  491. reg = < 0x03 >;
  492. #phy-cells = < 0x01 >;
  493. };
  494.  
  495. phy@4 {
  496. reg = < 0x04 >;
  497. #phy-cells = < 0x01 >;
  498. };
  499.  
  500. phy@5 {
  501. reg = < 0x05 >;
  502. #phy-cells = < 0x01 >;
  503. phandle = < 0x0f >;
  504. };
  505. };
  506.  
  507. mvebu-sar@18600 {
  508. compatible = "marvell,armada-380-core-clock";
  509. reg = < 0x18600 0x04 >;
  510. #clock-cells = < 0x01 >;
  511. phandle = < 0x04 >;
  512. };
  513.  
  514. mbus-controller@20000 {
  515. compatible = "marvell,mbus-controller";
  516. reg = < 0x20000 0x100 0x20180 0x20 0x20250 0x08 >;
  517. phandle = < 0x02 >;
  518. };
  519.  
  520. interrupt-controller@20a00 {
  521. compatible = "marvell,mpic";
  522. reg = < 0x20a00 0x2d0 0x21070 0x58 >;
  523. #interrupt-cells = < 0x01 >;
  524. #size-cells = < 0x01 >;
  525. interrupt-controller;
  526. msi-controller;
  527. interrupts = < 0x01 0x0f 0x04 >;
  528. phandle = < 0x01 >;
  529. };
  530.  
  531. timer@20300 {
  532. compatible = "marvell,armada-380-timer\0marvell,armada-xp-timer";
  533. reg = < 0x20300 0x30 0x21040 0x30 >;
  534. interrupts-extended = < 0x03 0x00 0x08 0x04 0x03 0x00 0x09 0x04 0x03 0x00 0x0a 0x04 0x03 0x00 0x0b 0x04 0x01 0x05 0x01 0x06 >;
  535. clocks = < 0x04 0x02 0x09 >;
  536. clock-names = "nbclk\0fixed";
  537. };
  538.  
  539. watchdog@20300 {
  540. compatible = "marvell,armada-380-wdt";
  541. reg = < 0x20300 0x34 0x20704 0x04 0x18260 0x04 >;
  542. clocks = < 0x04 0x02 0x09 >;
  543. clock-names = "nbclk\0fixed";
  544. interrupts-extended = < 0x03 0x00 0x40 0x04 0x03 0x00 0x09 0x04 >;
  545. };
  546.  
  547. cpurst@20800 {
  548. compatible = "marvell,armada-370-cpu-reset";
  549. reg = < 0x20800 0x10 >;
  550. };
  551.  
  552. mpcore-soc-ctrl@20d20 {
  553. compatible = "marvell,armada-380-mpcore-soc-ctrl";
  554. reg = < 0x20d20 0x6c >;
  555. };
  556.  
  557. coherency-fabric@21010 {
  558. compatible = "marvell,armada-380-coherency-fabric";
  559. reg = < 0x21010 0x1c >;
  560. };
  561.  
  562. pmsu@22000 {
  563. compatible = "marvell,armada-380-pmsu";
  564. reg = < 0x22000 0x1000 >;
  565. };
  566.  
  567. ethernet@70000 {
  568. compatible = "marvell,armada-370-neta";
  569. reg = < 0x70000 0x4000 >;
  570. interrupts-extended = < 0x01 0x08 >;
  571. clocks = < 0x0a 0x04 >;
  572. tx-csum-limit = < 0x2648 >;
  573. status = "okay";
  574. pinctrl-0 = < 0x0b >;
  575. pinctrl-names = "default";
  576. phy = < 0x0c >;
  577. phy-mode = "rgmii-id";
  578. buffer-manager = < 0x0d >;
  579. bm,pool-long = < 0x00 >;
  580. bm,pool-short = < 0x01 >;
  581. };
  582.  
  583. ethernet@30000 {
  584. compatible = "marvell,armada-370-neta";
  585. reg = < 0x30000 0x4000 >;
  586. interrupts-extended = < 0x01 0x0a >;
  587. clocks = < 0x0a 0x03 >;
  588. status = "okay";
  589. bm,pool-long = < 0x02 >;
  590. bm,pool-short = < 0x01 >;
  591. buffer-manager = < 0x0d >;
  592. phys = < 0x0e 0x01 >;
  593. phy-mode = "sgmii";
  594. phandle = < 0x15 >;
  595.  
  596. fixed-link {
  597. speed = < 0x3e8 >;
  598. full-duplex;
  599. };
  600. };
  601.  
  602. ethernet@34000 {
  603. compatible = "marvell,armada-370-neta";
  604. reg = < 0x34000 0x4000 >;
  605. interrupts-extended = < 0x01 0x0c >;
  606. clocks = < 0x0a 0x02 >;
  607. status = "okay";
  608. bm,pool-long = < 0x03 >;
  609. bm,pool-short = < 0x01 >;
  610. buffer-manager = < 0x0d >;
  611. managed = "in-band-status";
  612. phys = < 0x0f 0x02 >;
  613. phy-mode = "sgmii";
  614. sfp = < 0x10 >;
  615. };
  616.  
  617. usb@58000 {
  618. compatible = "marvell,orion-ehci";
  619. reg = < 0x58000 0x500 >;
  620. interrupts = < 0x00 0x12 0x04 >;
  621. clocks = < 0x0a 0x12 >;
  622. status = "okay";
  623. };
  624.  
  625. xor@60800 {
  626. compatible = "marvell,armada-380-xor\0marvell,orion-xor";
  627. reg = < 0x60800 0x100 0x60a00 0x100 >;
  628. clocks = < 0x0a 0x16 >;
  629. status = "okay";
  630.  
  631. xor00 {
  632. interrupts = < 0x00 0x16 0x04 >;
  633. dmacap,memcpy;
  634. dmacap,xor;
  635. };
  636.  
  637. xor01 {
  638. interrupts = < 0x00 0x17 0x04 >;
  639. dmacap,memcpy;
  640. dmacap,xor;
  641. dmacap,memset;
  642. };
  643. };
  644.  
  645. xor@60900 {
  646. compatible = "marvell,armada-380-xor\0marvell,orion-xor";
  647. reg = < 0x60900 0x100 0x60b00 0x100 >;
  648. clocks = < 0x0a 0x1c >;
  649. status = "okay";
  650.  
  651. xor10 {
  652. interrupts = < 0x00 0x41 0x04 >;
  653. dmacap,memcpy;
  654. dmacap,xor;
  655. };
  656.  
  657. xor11 {
  658. interrupts = < 0x00 0x42 0x04 >;
  659. dmacap,memcpy;
  660. dmacap,xor;
  661. dmacap,memset;
  662. };
  663. };
  664.  
  665. mdio@72004 {
  666. #address-cells = < 0x01 >;
  667. #size-cells = < 0x00 >;
  668. compatible = "marvell,orion-mdio";
  669. reg = < 0x72004 0x04 >;
  670. clocks = < 0x0a 0x04 >;
  671. pinctrl-0 = < 0x11 0x12 >;
  672. pinctrl-names = "default";
  673. status = "okay";
  674.  
  675. ethernet-phy@0 {
  676. marvell,reg-init = < 0x03 0x10 0x00 0x101e >;
  677. reg = < 0x00 >;
  678. phandle = < 0x0c >;
  679. };
  680.  
  681. switch@4 {
  682. compatible = "marvell,mv88e6085";
  683. #address-cells = < 0x01 >;
  684. #size-cells = < 0x00 >;
  685. reg = < 0x04 >;
  686. pinctrl-0 = < 0x13 0x14 >;
  687. pinctrl-names = "default";
  688.  
  689. ports {
  690. #address-cells = < 0x01 >;
  691. #size-cells = < 0x00 >;
  692.  
  693. port@0 {
  694. reg = < 0x00 >;
  695. label = "lan5";
  696. };
  697.  
  698. port@1 {
  699. reg = < 0x01 >;
  700. label = "lan4";
  701. };
  702.  
  703. port@2 {
  704. reg = < 0x02 >;
  705. label = "lan3";
  706. };
  707.  
  708. port@3 {
  709. reg = < 0x03 >;
  710. label = "lan2";
  711. };
  712.  
  713. port@4 {
  714. reg = < 0x04 >;
  715. label = "lan1";
  716. };
  717.  
  718. port@5 {
  719. reg = < 0x05 >;
  720. label = "cpu";
  721. ethernet = < 0x15 >;
  722.  
  723. fixed-link {
  724. speed = < 0x3e8 >;
  725. full-duplex;
  726. };
  727. };
  728.  
  729. port@6 {
  730. reg = < 0x06 >;
  731. label = "lan6";
  732.  
  733. fixed-link {
  734. speed = < 0x3e8 >;
  735. full-duplex;
  736. };
  737. };
  738. };
  739. };
  740. };
  741.  
  742. crypto@90000 {
  743. compatible = "marvell,armada-38x-crypto";
  744. reg = < 0x90000 0x10000 >;
  745. reg-names = "regs";
  746. interrupts = < 0x00 0x13 0x04 0x00 0x14 0x04 >;
  747. clocks = < 0x0a 0x17 0x0a 0x15 0x0a 0x0e 0x0a 0x10 >;
  748. clock-names = "cesa0\0cesa1\0cesaz0\0cesaz1";
  749. marvell,crypto-srams = < 0x16 0x17 >;
  750. marvell,crypto-sram-size = < 0x800 >;
  751. };
  752.  
  753. rtc@a3800 {
  754. compatible = "marvell,armada-380-rtc";
  755. reg = < 0xa3800 0x20 0x184a0 0x0c >;
  756. reg-names = "rtc\0rtc-soc";
  757. interrupts = < 0x00 0x15 0x04 >;
  758. status = "okay";
  759. };
  760.  
  761. sata@a8000 {
  762. compatible = "marvell,armada-380-ahci";
  763. reg = < 0xa8000 0x2000 >;
  764. interrupts = < 0x00 0x1a 0x04 >;
  765. clocks = < 0x0a 0x0f >;
  766. status = "okay";
  767. };
  768.  
  769. bm@c8000 {
  770. compatible = "marvell,armada-380-neta-bm";
  771. reg = < 0xc8000 0xac >;
  772. clocks = < 0x0a 0x0d >;
  773. internal-mem = < 0x18 >;
  774. status = "okay";
  775. phandle = < 0x0d >;
  776. };
  777.  
  778. sata@e0000 {
  779. compatible = "marvell,armada-380-ahci";
  780. reg = < 0xe0000 0x2000 >;
  781. interrupts = < 0x00 0x1c 0x04 >;
  782. clocks = < 0x0a 0x1e >;
  783. status = "okay";
  784. };
  785.  
  786. clock@e4250 {
  787. compatible = "marvell,armada-380-corediv-clock";
  788. reg = < 0xe4250 0x0c >;
  789. #clock-cells = < 0x01 >;
  790. clocks = < 0x19 >;
  791. clock-output-names = "nand";
  792. phandle = < 0x1a >;
  793. };
  794.  
  795. thermal@e8078 {
  796. compatible = "marvell,armada380-thermal";
  797. reg = < 0xe4078 0x04 0xe4070 0x08 >;
  798. status = "okay";
  799. };
  800.  
  801. nand-controller@d0000 {
  802. compatible = "marvell,armada370-nand-controller";
  803. reg = < 0xd0000 0x54 >;
  804. #address-cells = < 0x01 >;
  805. #size-cells = < 0x00 >;
  806. interrupts = < 0x00 0x54 0x04 >;
  807. clocks = < 0x1a 0x00 >;
  808. status = "disabled";
  809. };
  810.  
  811. sdhci@d8000 {
  812. compatible = "marvell,armada-380-sdhci";
  813. reg-names = "sdhci\0mbus\0conf-sdio3";
  814. reg = < 0xd8000 0x1000 0xdc000 0x100 0x18454 0x04 >;
  815. interrupts = < 0x00 0x19 0x04 >;
  816. clocks = < 0x0a 0x11 >;
  817. mrvl,clk-delay-cycles = < 0x1f >;
  818. status = "okay";
  819. bus-width = < 0x04 >;
  820. cd-gpios = < 0x1b 0x14 0x01 >;
  821. no-1-8-v;
  822. pinctrl-0 = < 0x1c 0x1d >;
  823. pinctrl-names = "default";
  824. vmmc-supply = < 0x1e >;
  825. wp-inverted;
  826. };
  827.  
  828. usb3@f0000 {
  829. compatible = "marvell,armada-380-xhci";
  830. reg = < 0xf0000 0x4000 0xf4000 0x4000 >;
  831. interrupts = < 0x00 0x10 0x04 >;
  832. clocks = < 0x0a 0x09 >;
  833. status = "okay";
  834. };
  835.  
  836. usb3@f8000 {
  837. compatible = "marvell,armada-380-xhci";
  838. reg = < 0xf8000 0x4000 0xfc000 0x4000 >;
  839. interrupts = < 0x00 0x11 0x04 >;
  840. clocks = < 0x0a 0x0a >;
  841. status = "okay";
  842. };
  843. };
  844.  
  845. sa-sram0 {
  846. compatible = "mmio-sram";
  847. reg = < 0x9190000 0x00 0x800 >;
  848. clocks = < 0x0a 0x17 >;
  849. #address-cells = < 0x01 >;
  850. #size-cells = < 0x01 >;
  851. ranges = < 0x00 0x9190000 0x00 0x800 >;
  852. phandle = < 0x16 >;
  853. };
  854.  
  855. sa-sram1 {
  856. compatible = "mmio-sram";
  857. reg = < 0x9150000 0x00 0x800 >;
  858. clocks = < 0x0a 0x15 >;
  859. #address-cells = < 0x01 >;
  860. #size-cells = < 0x01 >;
  861. ranges = < 0x00 0x9150000 0x00 0x800 >;
  862. phandle = < 0x17 >;
  863. };
  864.  
  865. bm-bppi {
  866. compatible = "mmio-sram";
  867. reg = < 0xc040000 0x00 0x100000 >;
  868. ranges = < 0x00 0xc040000 0x00 0x100000 >;
  869. #address-cells = < 0x01 >;
  870. #size-cells = < 0x01 >;
  871. clocks = < 0x0a 0x0d >;
  872. no-memory-wc;
  873. status = "okay";
  874. phandle = < 0x18 >;
  875. };
  876.  
  877. spi@10600 {
  878. compatible = "marvell,armada-380-spi\0marvell,orion-spi";
  879. reg = < 0xf0010000 0x10600 0x50 >;
  880. #address-cells = < 0x01 >;
  881. #size-cells = < 0x00 >;
  882. cell-index = < 0x00 >;
  883. interrupts = < 0x00 0x01 0x04 >;
  884. clocks = < 0x04 0x00 >;
  885. status = "disabled";
  886. };
  887.  
  888. spi@10680 {
  889. compatible = "marvell,armada-380-spi\0marvell,orion-spi";
  890. reg = < 0xf0010000 0x10680 0x50 >;
  891. #address-cells = < 0x01 >;
  892. #size-cells = < 0x00 >;
  893. cell-index = < 0x01 >;
  894. interrupts = < 0x00 0x3f 0x04 >;
  895. clocks = < 0x04 0x00 >;
  896. status = "okay";
  897. pinctrl-0 = < 0x1f 0x20 0x21 >;
  898. pinctrl-names = "default";
  899.  
  900. spi-flash@0 {
  901. #address-cells = < 0x01 >;
  902. #size-cells = < 0x01 >;
  903. compatible = "w25q32\0jedec,spi-nor";
  904. reg = < 0x00 >;
  905. spi-max-frequency = < 0x2dc6c0 >;
  906. };
  907. };
  908.  
  909. pcie {
  910. compatible = "marvell,armada-370-pcie";
  911. status = "okay";
  912. device_type = "pci";
  913. #address-cells = < 0x03 >;
  914. #size-cells = < 0x02 >;
  915. msi-parent = < 0x01 >;
  916. bus-range = < 0x00 0xff >;
  917. ranges = < 0x82000000 0x00 0x80000 0xf0010000 0x80000 0x00 0x2000 0x82000000 0x00 0x40000 0xf0010000 0x40000 0x00 0x2000 0x82000000 0x00 0x44000 0xf0010000 0x44000 0x00 0x2000 0x82000000 0x00 0x48000 0xf0010000 0x48000 0x00 0x2000 0x82000000 0x01 0x00 0x8e80000 0x00 0x01 0x00 0x81000000 0x01 0x00 0x8e00000 0x00 0x01 0x00 0x82000000 0x02 0x00 0x4e80000 0x00 0x01 0x00 0x81000000 0x02 0x00 0x4e00000 0x00 0x01 0x00 0x82000000 0x03 0x00 0x4d80000 0x00 0x01 0x00 0x81000000 0x03 0x00 0x4d00000 0x00 0x01 0x00 0x82000000 0x04 0x00 0x4b80000 0x00 0x01 0x00 0x81000000 0x04 0x00 0x4b00000 0x00 0x01 0x00 >;
  918.  
  919. pcie@1,0 {
  920. device_type = "pci";
  921. assigned-addresses = < 0x82000800 0x00 0x80000 0x00 0x2000 >;
  922. reg = < 0x800 0x00 0x00 0x00 0x00 >;
  923. #address-cells = < 0x03 >;
  924. #size-cells = < 0x02 >;
  925. #interrupt-cells = < 0x01 >;
  926. ranges = < 0x82000000 0x00 0x00 0x82000000 0x01 0x00 0x01 0x00 0x81000000 0x00 0x00 0x81000000 0x01 0x00 0x01 0x00 >;
  927. bus-range = < 0x00 0xff >;
  928. interrupt-map-mask = < 0x00 0x00 0x00 0x00 >;
  929. interrupt-map = < 0x00 0x00 0x00 0x00 0x03 0x00 0x1d 0x04 >;
  930. marvell,pcie-port = < 0x00 >;
  931. marvell,pcie-lane = < 0x00 >;
  932. clocks = < 0x0a 0x08 >;
  933. status = "disabled";
  934. };
  935.  
  936. pcie@2,0 {
  937. device_type = "pci";
  938. assigned-addresses = < 0x82000800 0x00 0x40000 0x00 0x2000 >;
  939. reg = < 0x1000 0x00 0x00 0x00 0x00 >;
  940. #address-cells = < 0x03 >;
  941. #size-cells = < 0x02 >;
  942. #interrupt-cells = < 0x01 >;
  943. ranges = < 0x82000000 0x00 0x00 0x82000000 0x02 0x00 0x01 0x00 0x81000000 0x00 0x00 0x81000000 0x02 0x00 0x01 0x00 >;
  944. bus-range = < 0x00 0xff >;
  945. interrupt-map-mask = < 0x00 0x00 0x00 0x00 >;
  946. interrupt-map = < 0x00 0x00 0x00 0x00 0x03 0x00 0x21 0x04 >;
  947. marvell,pcie-port = < 0x01 >;
  948. marvell,pcie-lane = < 0x00 >;
  949. clocks = < 0x0a 0x05 >;
  950. status = "okay";
  951. reset-gpios = < 0x22 0x01 0x01 >;
  952. };
  953.  
  954. pcie@3,0 {
  955. device_type = "pci";
  956. assigned-addresses = < 0x82000800 0x00 0x44000 0x00 0x2000 >;
  957. reg = < 0x1800 0x00 0x00 0x00 0x00 >;
  958. #address-cells = < 0x03 >;
  959. #size-cells = < 0x02 >;
  960. #interrupt-cells = < 0x01 >;
  961. ranges = < 0x82000000 0x00 0x00 0x82000000 0x03 0x00 0x01 0x00 0x81000000 0x00 0x00 0x81000000 0x03 0x00 0x01 0x00 >;
  962. bus-range = < 0x00 0xff >;
  963. interrupt-map-mask = < 0x00 0x00 0x00 0x00 >;
  964. interrupt-map = < 0x00 0x00 0x00 0x00 0x03 0x00 0x46 0x04 >;
  965. marvell,pcie-port = < 0x02 >;
  966. marvell,pcie-lane = < 0x00 >;
  967. clocks = < 0x0a 0x06 >;
  968. status = "okay";
  969. reset-gpios = < 0x22 0x02 0x01 >;
  970. };
  971.  
  972. pcie@4,0 {
  973. device_type = "pci";
  974. assigned-addresses = < 0x82000800 0x00 0x48000 0x00 0x2000 >;
  975. reg = < 0x2000 0x00 0x00 0x00 0x00 >;
  976. #address-cells = < 0x03 >;
  977. #size-cells = < 0x02 >;
  978. #interrupt-cells = < 0x01 >;
  979. ranges = < 0x82000000 0x00 0x00 0x82000000 0x04 0x00 0x01 0x00 0x81000000 0x00 0x00 0x81000000 0x04 0x00 0x01 0x00 >;
  980. bus-range = < 0x00 0xff >;
  981. interrupt-map-mask = < 0x00 0x00 0x00 0x00 >;
  982. interrupt-map = < 0x00 0x00 0x00 0x00 0x03 0x00 0x47 0x04 >;
  983. marvell,pcie-port = < 0x03 >;
  984. marvell,pcie-lane = < 0x00 >;
  985. clocks = < 0x0a 0x07 >;
  986. status = "disabled";
  987. };
  988. };
  989. };
  990.  
  991. clocks {
  992.  
  993. mainpll {
  994. compatible = "fixed-clock";
  995. #clock-cells = < 0x00 >;
  996. clock-frequency = < 0x3b9aca00 >;
  997. phandle = < 0x19 >;
  998. };
  999.  
  1000. oscillator {
  1001. compatible = "fixed-clock";
  1002. #clock-cells = < 0x00 >;
  1003. clock-frequency = < 0x17d7840 >;
  1004. phandle = < 0x09 >;
  1005. };
  1006. };
  1007.  
  1008. cpus {
  1009. #address-cells = < 0x01 >;
  1010. #size-cells = < 0x00 >;
  1011. enable-method = "marvell,armada-380-smp";
  1012.  
  1013. cpu@0 {
  1014. device_type = "cpu";
  1015. compatible = "arm,cortex-a9";
  1016. reg = < 0x00 >;
  1017. };
  1018.  
  1019. cpu@1 {
  1020. device_type = "cpu";
  1021. compatible = "arm,cortex-a9";
  1022. reg = < 0x01 >;
  1023. };
  1024. };
  1025.  
  1026. memory {
  1027. device_type = "memory";
  1028. reg = < 0x00 0x10000000 >;
  1029. };
  1030.  
  1031. chosen {
  1032. stdout-path = "serial0:115200n8";
  1033. };
  1034.  
  1035. regulator-3p3v {
  1036. compatible = "regulator-fixed";
  1037. regulator-name = "3P3V";
  1038. regulator-min-microvolt = < 0x325aa0 >;
  1039. regulator-max-microvolt = < 0x325aa0 >;
  1040. regulator-always-on;
  1041. phandle = < 0x1e >;
  1042. };
  1043.  
  1044. sfp {
  1045. compatible = "sff,sfp";
  1046. i2c-bus = < 0x23 >;
  1047. los-gpio = < 0x22 0x0c 0x00 >;
  1048. mod-def0-gpio = < 0x22 0x0f 0x01 >;
  1049. tx-disable-gpio = < 0x22 0x0e 0x00 >;
  1050. tx-fault-gpio = < 0x22 0x0d 0x00 >;
  1051. maximum-power-milliwatt = < 0x7d0 >;
  1052. phandle = < 0x10 >;
  1053. };
  1054.  
  1055. gpio-keys {
  1056. compatible = "gpio-keys";
  1057. pinctrl-0 = < 0x24 >;
  1058. pinctrl-names = "default";
  1059.  
  1060. button_0 {
  1061. label = "Rear Button";
  1062. gpios = < 0x25 0x02 0x01 >;
  1063. linux,can-disable;
  1064. linux,code = < 0x100 >;
  1065. };
  1066. };
  1067. };
  1068.  
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!