library IEEE;
use IEEE.STD_LOGIC_1164.all;
--------------------------------------------------
entity vand5 is
    port (i1 : in  std_logic;
            i2 : in  std_logic;
            i3 : in  std_logic;
            i4 : in  std_logic;
            i5 : in  std_logic;
            o : out  std_logic);
end vand5;
--------------------------------------------------
architecture df1 of vand5 is
begin
    o <= i1 and i2 and i3 and i4 and i5;
end df1;