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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- entity board is
- Port ( clk : in STD_LOGIC;
- btn : in STD_LOGIC_VECTOR (4 downto 0);
- sw : in STD_LOGIC_VECTOR (15 downto 0);
- led : out STD_LOGIC_VECTOR (15 downto 0);
- an : out STD_LOGIC_VECTOR (3 downto 0);
- cat : out STD_LOGIC_VECTOR (6 downto 0);
- tx : out STD_LOGIC;
- rx : in STD_LOGIC);
- end board;
- architecture Behavioral of board is
- signal display : STD_LOGIC_VECTOR(15 downto 0);
- signal en : STD_LOGIC_VECTOR(4 downto 0); -- FOR MPG
- type state_type is (start, idle, data, stop);
- signal state : state_type := idle;
- signal tx_data : STD_LOGIC_VECTOR(7 downto 0);
- signal tx_en : STD_LOGIC := '0';
- signal rst : STD_LOGIC;
- signal baud_en : STD_LOGIC;
- signal baud_cnt : STD_LOGIC_VECTOR(13 downto 0);
- signal tx_rdy : STD_LOGIC;
- signal clk_div : STD_LOGIC;
- signal bit_cnt : STD_LOGIC_VECTOR(2 downto 0);
- component mpg is
- Port( clk : in STD_LOGIC;
- btn : in STD_LOGIC_VECTOR (4 downto 0);
- enable : out STD_LOGIC_VECTOR (4 downto 0));
- end component;
- component seven_segments is
- Port ( clk : in STD_LOGIC;
- digit0, digit1, digit2, digit3 : in STD_LOGIC_VECTOR(3 downto 0);
- catod : out STD_LOGIC_VECTOR (6 downto 0);
- anod : out STD_LOGIC_VECTOR (3 downto 0));
- end component;
- begin
- led <= bit_cnt & sw(12 downto 0);
- rst <= en(1);
- tx_data <= x"33";-- sw(7 downto 0);
- mpgU : mpg Port map(
- clk => clk,
- btn => btn,
- enable => en
- );
- ssd: seven_segments Port map(
- digit0 => display(3 downto 0),
- digit1 => display(7 downto 4),
- digit2 => display(11 downto 8),
- digit3 => display(15 downto 12),
- clk => clk,
- catod => cat,
- anod => an
- );
- baud: process(clk)
- begin
- if rising_edge(clk) then
- if baud_cnt = 10415 then
- baud_en <= '1';
- baud_cnt <= (others => '0');
- else
- baud_cnt <= baud_cnt + 1;
- baud_en <= '0';
- end if;
- end if;
- end process;
- process(clk, en(0), baud_en)
- begin
- if rising_edge(clk) then
- if en(0) = '1' then
- tx_en <= '1';
- elsif baud_en = '1' then
- tx_en <= '0';
- end if;
- end if;
- end process;
- -- when en(0) = '1' else '0' when baud_en = '1';
- process(state, bit_cnt, tx_data)
- begin
- case state is
- when idle => tx <= '1';
- tx_rdy <= '1';
- when start => tx <= '0';
- tx_rdy <= '0';
- when data => tx <= tx_data(conv_integer(bit_cnt));
- tx_rdy <= '0';
- when stop => tx <= '1';
- tx_rdy <= '0';
- end case;
- end process;
- process(baud_en, clk, rst, tx_en, state)
- begin
- if rising_edge(clk) then
- if baud_en = '1' then
- case state is
- when idle =>
- if tx_en = '1' then
- state <= start;
- bit_cnt <= "000";
- else
- state <= idle;
- bit_cnt <= "000";
- end if;
- when start =>
- state <= data;
- bit_cnt <= "000";
- when data =>
- if bit_cnt = "111" then
- state <= stop;
- bit_cnt <= "000";
- else
- bit_cnt <= bit_cnt + 1;
- state <= stop;
- end if;
- when stop =>
- state <= idle;
- bit_cnt <= "000";
- end case;
- end if;
- end if;
- end process;
- end Behavioral;
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