library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;

USE work.procmem_definitions.ALL;

entity memory is
    Port (
    clk:in std_logic;
    address: in std_ulogic_vector(width-1 downto 0);
    memread: in std_logic;
    wr_en: in std_logic;
    writedata: in std_ulogic_vector(width-1 downto 0);
    read:out std_ulogic_vector(width-1 downto 0));
end memory;

architecture Behavioral of memory is

type ram is array(0 to width-1) of std_ulogic_vector(0 to width-1);
signal memory: ram:=(
    B"101011_00001_00000_00000_00000_000011", -- store 3 in r1
    B"101011_00010_00000_00000_00000_000010", -- store 2 in r2
    B"000000_00001_00001_00010_00000_100000", -- add r1 = r1 + r2
    B"000000_00010_00001_00010_00000_100010", -- sub r3 = r1 -r2
    others =>(others=>'0'));

begin

    process(clk, address, wr_en, writedata)
    begin
        if rising_edge(clk)then
            if memread = '1' then
                read <= memory(to_integer(unsigned(address)));
            else if wr_en = '1' then
                memory(to_integer(unsigned(address))) <= writedata;
            end if;
            end if;
        end if;
    end process;

end Behavioral;