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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. USE IEEE.numeric_std.ALL;
  4.  
  5. USE work.procmem_definitions.ALL;
  6.  
  7. entity memory is
  8.     Port (
  9.     clk:in std_logic;
  10.     address: in std_ulogic_vector(width-1 downto 0);
  11.     memread: in std_logic;
  12.     wr_en: in std_logic;
  13.     writedata: in std_ulogic_vector(width-1 downto 0);
  14.     read:out std_ulogic_vector(width-1 downto 0));
  15. end memory;
  16.  
  17. architecture Behavioral of memory is
  18.  
  19. type ram is array(0 to width-1) of std_ulogic_vector(0 to width-1);
  20. signal memory: ram:=(
  21.     B"101011_00001_00000_00000_00000_000011", -- store 3 in r1
  22.     B"101011_00010_00000_00000_00000_000010", -- store 2 in r2
  23.     B"000000_00001_00001_00010_00000_100000", -- add r1 = r1 + r2
  24.     B"000000_00010_00001_00010_00000_100010", -- sub r3 = r1 -r2
  25.     others =>(others=>'0'));
  26.  
  27. begin
  28.  
  29.     process(clk, address, wr_en, writedata)
  30.     begin
  31.         if rising_edge(clk)then
  32.             if memread = '1' then
  33.                 read <= memory(to_integer(unsigned(address)));
  34.             else if wr_en = '1' then
  35.                 memory(to_integer(unsigned(address))) <= writedata;
  36.             end if;
  37.             end if;
  38.         end if;
  39.     end process;
  40.  
  41. end Behavioral;
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