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Jan 31st, 2014
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  1. entity sdram_controller is
  2.     generic (
  3.         CLK_PERIOD : integer := 10; -- in ns
  4.         INIT_TIME : integer := 150000; -- in ns
  5.         INIT_PCHG : integer := 10; -- num of iterations
  6.         INIT_AREF : integer := 10; -- num of iterations
  7.         AREF_COUNT : integer := 5000; -- in ns
  8.         BANK_WIDTH : integer := 2; -- in bits
  9.         ROW_WIDTH : integer := 12; -- in bits
  10.         COL_WIDTH : integer := 8; -- in bits
  11.         DATA_WIDTH : integer := 16; -- in bits
  12.         ADDR_WIDTH : integer := 22; -- in bits
  13.         BUF_WIDTH : integer := 12; -- in bits
  14.  
  15.         -- sdram time parameters
  16.         tCK : integer := 10; -- the same as CLK_PERIOD
  17.         tRP : integer := 20; -- idle after precharge
  18.         tRC : integer := 70; -- idle after auto refresh
  19.         tRCD : integer := 20 -- activate to r/w
  20.     );
  21.     port (
  22.         clock : in std_logic;
  23.         reset : in std_logic;
  24.  
  25.         -- client 0
  26.         clock0 : in std_logic;
  27.         strobe0 : in std_logic;
  28.         wr0 : in std_logic;
  29.         addr0 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
  30.         nwords0 : in std_logic_vector(BUF_WIDTH - 1 downto 0);
  31.         busy0 : out std_logic;
  32.  
  33.         buf_clock_0 : out std_logic;
  34.         buf_wr_0 : out std_logic;
  35.         buf_addr_0 : out std_logic_vector(BUF_WIDTH - 1 downto 0);
  36.         buf_data_i_0 : out std_logic_vector(DATA_WIDTH - 1 downto 0);
  37.         buf_data_o_0 : in std_logic_vector(DATA_WIDTH - 1 downto 0);
  38.  
  39.         -- client 1
  40.         clock1 : in std_logic;
  41.         strobe1 : in std_logic;
  42.         wr1 : in std_logic;
  43.         addr1 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
  44.         nwords1 : in std_logic_vector(BUF_WIDTH - 1 downto 0);
  45.         busy1 : out std_logic;
  46.  
  47.         buf_clock_1 : out std_logic;
  48.         buf_wr_1 : out std_logic;
  49.         buf_addr_1 : out std_logic_vector(BUF_WIDTH - 1 downto 0);
  50.         buf_data_i_1 : out std_logic_vector(DATA_WIDTH - 1 downto 0);
  51.         buf_data_o_1 : in std_logic_vector(DATA_WIDTH - 1 downto 0);
  52.  
  53.         -- client 2
  54.         clock2 : in std_logic;
  55.         strobe2 : in std_logic;
  56.         wr2 : in std_logic;
  57.         addr2 : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
  58.         nwords2 : in std_logic_vector(BUF_WIDTH - 1 downto 0);
  59.         busy2 : out std_logic;
  60.  
  61.         buf_clock_2 : out std_logic;
  62.         buf_wr_2 : out std_logic;
  63.         buf_addr_2 : out std_logic_vector(BUF_WIDTH - 1 downto 0);
  64.         buf_data_i_2 : out std_logic_vector(DATA_WIDTH - 1 downto 0);
  65.         buf_data_o_2 : in std_logic_vector(DATA_WIDTH - 1 downto 0);
  66.  
  67.  
  68.         -- sdram interface
  69.         ram_clock : out std_logic;
  70.         ram_cke : out std_logic;
  71.         ram_ncs : out std_logic;
  72.         ram_nras : out std_logic;
  73.         ram_ncas : out std_logic;
  74.         ram_nwe : out std_logic;
  75.         ram_bs : out std_logic_vector(BANK_WIDTH - 1 downto 0);
  76.         ram_a : out std_logic_vector(ROW_WIDTH - 1 downto 0);
  77.         ram_dqm : out std_logic_vector(DATA_WIDTH / 8 - 1 downto 0);
  78.         ram_dq : inout std_logic_vector(DATA_WIDTH - 1 downto 0)
  79.     );
  80. end sdram_controller;
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