library ieee;
use ieee.std_logic_1164.all;

entity TimesTen is
port(
X:in std_logic_vector(5 downto 0);
TenX:out std_logic_vector(9 downto 0));
end entity TimesTen;

Architecture behaviour of TimesTen is

signal a,b,Cout:std_logic_vector(9 downto 0);
component fulladder
port(A,B,Cin:in std_logic;
	S,C:out std_logic);
	end component;
begin
a(9 downto 7)<= "000";
a(6 downto 1)<=X(5 downto 0);
a(0)<= '0';
b(9)<= '0';
b(8 downto 3)<= X(5 downto 0);
b(2 downto 0)<= "000";
FA1:fulladder port map(A=>a(0), B=>b(0), Cin=> '0', S=>TenX(0), C=>Cout(0));
FA2:fulladder port map(A=>a(1), B=>b(1), Cin=> Cout(0), S=>TenX(1), C=>Cout(1));
FA3:fulladder port map(A=>a(2), B=>b(2), Cin=> Cout(1), S=>TenX(2), C=>Cout(2));
FA4:fulladder port map(A=>a(3), B=>b(3), Cin=> Cout(2), S=>TenX(3), C=>Cout(3));
FA5:fulladder port map(A=>a(4), B=>b(4), Cin=> Cout(3), S=>TenX(4), C=>Cout(4));
FA6:fulladder port map(A=>a(5), B=>b(5), Cin=> Cout(4), S=>TenX(5), C=>Cout(5));
FA7:fulladder port map(A=>a(6), B=>b(6), Cin=> Cout(5), S=>TenX(6), C=>Cout(6));
FA8:fulladder port map(A=>a(7), B=>b(7), Cin=> Cout(6), S=>TenX(7), C=>Cout(7));
FA9:fulladder port map(A=>a(8), B=>b(8), Cin=> Cout(7), S=>TenX(8), C=>Cout(8));
FA10:fulladder port map(A=>a(9), B=>b(9), Cin=> Cout(8), S=>TenX(9), C=>Cout(9));


end architecture behaviour;