Guest User

Untitled

a guest
Jun 20th, 2014
853
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. /dts-v1/;
  2.  
  3. / {
  4. model = "Xilinx Zynq ZED";
  5. compatible = "xlnx,zynq-zc702";
  6. #address-cells = <0x1>;
  7. #size-cells = <0x1>;
  8. interrupt-parent = <0x1>;
  9.  
  10. memory {
  11. device_type = "memory";
  12. reg = <0x000000000 0x20000000>;
  13. };
  14. chosen {
  15. // bootargs = "console=ttyPS0,115200 root=/dev/ram rw initrd=0x1100000,33M ip=:::::eth0:dhcp earlyprintk";
  16. bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait devtmpfs.mount=0";
  17. linux,stdout-path = "/amba@0/uart@E0001000";
  18. };
  19.  
  20. pmu {
  21. compatible = "arm,cortex-a9-pmu";
  22. interrupts = <0 5 4>, <0 6 4>;
  23. interrupt-parent = <&gic>;
  24. };
  25.  
  26. amba@0 {
  27. compatible = "simple-bus";
  28. #address-cells = <0x1>;
  29. #size-cells = <0x1>;
  30. ranges;
  31.  
  32. gic: intc@f8f01000 {
  33. interrupt-controller;
  34. compatible = "arm,cortex-a9-gic";
  35. #interrupt-cells = <3>;
  36. reg = < 0xf8f01000 0x1000 >,
  37. < 0xf8f00100 0x0100 >;
  38. };
  39.  
  40. pl310@f8f02000 {
  41. compatible = "arm,pl310-cache";
  42. cache-unified;
  43. cache-level = <2>;
  44. reg = <0xf8f02000 0x1000>;
  45. arm,data-latency = <3 2 2>;
  46. arm,tag-latency = <2 2 2>;
  47. };
  48.  
  49. uart@e0001000 {
  50. compatible = "xlnx,ps7-uart-1.00.a";
  51. reg = <0xe0001000 0x1000>;
  52. interrupts = < 0 50 0 >;
  53. interrupt-parent = <&gic>;
  54. clock = <50000000>;
  55. };
  56.  
  57. slcr: slcr@f8000000 {
  58. compatible = "xlnx,zynq-slcr";
  59. reg = <0xF8000000 0x1000>;
  60.  
  61. clocks {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. armpll: armpll {
  65. #clock-cells = <0>;
  66. clock-output-names = "armpll";
  67. clocks = <&ps_clk>;
  68. compatible = "xlnx,zynq-pll";
  69. lockbit = <0>;
  70. reg = < 0x100 0x110 0x10c >;
  71. } ;
  72. ddrpll: ddrpll {
  73. #clock-cells = <0>;
  74. clock-output-names = "ddrpll";
  75. clocks = <&ps_clk>;
  76. compatible = "xlnx,zynq-pll";
  77. lockbit = <1>;
  78. reg = < 0x104 0x114 0x10c >;
  79. } ;
  80. iopll: iopll {
  81. #clock-cells = <0>;
  82. clock-output-names = "iopll";
  83. clocks = <&ps_clk>;
  84. compatible = "xlnx,zynq-pll";
  85. lockbit = <2>;
  86. reg = < 0x108 0x118 0x10c >;
  87. } ;
  88. ps_clk: ps_clk {
  89. #clock-cells = <0>;
  90. clock-frequency = <33333333>;
  91. clock-output-names = "ps_clk";
  92. compatible = "fixed-clock";
  93. } ;
  94. };
  95. };
  96.  
  97. timer@0xf8001000 {
  98. compatible = "xlnx,ps7-ttc-1.00.a";
  99. reg = <0xf8001000 0x1000>;
  100. interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
  101. interrupt-parent = <&gic>;
  102. };
  103.  
  104. timer@f8f00600 {
  105. compatible = "arm,cortex-a9-twd-timer";
  106. reg = <0xf8f00600 0x20>;
  107. interrupts = <1 13 0x301>;
  108. interrupt-parent = <&gic>;
  109. };
  110.  
  111. swdt@f8005000 {
  112. device_type = "watchdog";
  113. compatible = "xlnx,ps7-wdt-1.00.a";
  114. reg = <0xf8005000 0x100>;
  115. interrupts = <0 9 4>;
  116. interrupt-parent = <&gic>;
  117. reset = <0>;
  118. timeout = <10>;
  119. };
  120.  
  121. scuwdt@f8f00620 {
  122. device_type = "watchdog";
  123. compatible = "arm,mpcore_wdt";
  124. reg = <0xf8f00620 0x20>;
  125. clock-frequency = <333333333>;
  126. reset = <1>;
  127. };
  128.  
  129. eth@e000b000 {
  130. compatible = "xlnx,ps7-ethernet-1.00.a";
  131. reg = <0xe000b000 0x1000>;
  132. interrupts = <0 22 0>;
  133. interrupt-parent = <&gic>;
  134. phy-handle = <&phy0>;
  135. phy-mode = "rgmii-id";
  136. #address-cells = <0x1>;
  137. #size-cells = <0x0>;
  138.  
  139. phy0: phy@0 {
  140. compatible = "marvell,88e1510";
  141. device_type = "ethernet-phy";
  142. reg = <0x0>;
  143. marvell,reg-init=<3 16 0xff00 0x1e 3 17 0xfff0 0x0a>;
  144. };
  145. };
  146.  
  147. /*gpio: gpio@e000a000 {
  148. compatible = "xlnx,ps7-gpio-1.00.a";
  149. reg = <0xe000a000 0x1000>;
  150. interrupts = <0 20 0>;
  151. interrupt-parent = <&gic>;
  152. gpio-controller;
  153. #gpio-cells = <2>;
  154. };*/
  155.  
  156. /* axi_iic_0: i2c@41600000 {
  157. compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a";
  158. interrupt-parent = <&gic>;
  159. interrupts = < 0 56 0x4 >;
  160. reg = < 0x41600000 0x10000 >;
  161.  
  162. #size-cells = <0>;
  163. #address-cells = <1>;
  164.  
  165. adv7511: adv7511@39 {
  166. compatible = "adi,adv7511";
  167. reg = <0x39>;
  168.  
  169. adi,input-style = <0x02>;
  170. adi,input-id = <0x01>;
  171. adi,input-color-depth = <0x3>;
  172. adi,sync-pulse = <0x03>;
  173. adi,bit-justification = <0x01>;
  174. adi,up-conversion = <0x00>;
  175. adi,timing-generation-sequence = <0x00>;
  176. adi,vsync-polarity = <0x02>;
  177. adi,hsync-polarity = <0x02>;
  178. adi,tdms-clock-inversion;
  179. adi,clock-delay = <0x03>;
  180. };
  181. };*/
  182.  
  183. sdhci@e0100000 {
  184. compatible = "xlnx,ps7-sdhci-1.00.a";
  185. reg = <0xe0100000 0x1000>;
  186. interrupts = <0 24 0>;
  187. interrupt-parent = <&gic>;
  188. clock-frequency = <50000000>;
  189. };
  190.  
  191. /*usb@e0002000 {
  192. compatible = "xlnx,ps7-usb-1.00.a";
  193. reg = <0xe0002000 0x1000>;
  194. interrupts = <0 21 4>;
  195. interrupt-parent = <&gic>;
  196. dr_mode = "host";
  197. phy_type = "ulpi";
  198. xlnx,usb-reset = <0xffffffff>;
  199. };*/
  200.  
  201. /*qspi0: spi@e000d000 {
  202. compatible = "xlnx,ps7-qspi-1.00.a";
  203. reg = <0xE000D000 0x1000>;
  204. interrupts = <0 19 0>;
  205. interrupt-parent = <&gic>;
  206. speed-hz = <200000000>;
  207. bus-num = <1>;
  208. num-chip-select = <1>;
  209. is-dual = <0>;
  210. };*/
  211.  
  212. /*devcfg@f8007000 {
  213. compatible = "xlnx,ps7-dev-cfg-1.00.a";
  214. reg = <0xf8007000 0x1000>;
  215. interrupts = <0 8 0>;
  216. interrupt-parent = <&gic>;
  217. };*/
  218.  
  219. /*axi_dma_0: axidma@40400000 {
  220. compatible = "xlnx,axi-dma";
  221. #address-cells = <1>;
  222. #size-cells = <1>;
  223. #dma-cells = <1>;
  224. #dma-channels = <1>;
  225. reg = < 0x40400000 0x1000 >;
  226. xlnx,sg-include-stscntrl-strm = <0x0>;
  227. dma-channel@40400000 {
  228. compatible = "xlnx,axi-dma-mm2s-channel";
  229. interrupts = < 0 58 0x4 >;
  230. xlnx,datawidth = <0x20>;
  231. xlnx,include-dre = <0x0>;
  232. };
  233. };*/
  234.  
  235. /*axi_vdma_0: axivdma@43000000 {
  236. compatible = "xlnx,axi-vdma";
  237. #address-cells = <1>;
  238. #size-cells = <1>;
  239. #dma-cells = <1>;
  240. #dma-channels = <1>;
  241. reg = <0x43000000 0x1000>;
  242. xlnx,include-sg = <0x0>;
  243. xlnx,num-fstores = <0x3>;
  244. dma-channel@7e200000 {
  245. compatible = "xlnx,axi-vdma-mm2s-channel";
  246. interrupts = <0 59 0x4>;
  247. xlnx,datawidth = <0x40>;
  248. xlnx,genlock-mode = <0x0>;
  249. xlnx,include-dre = <0x0>;
  250. };
  251. };*/
  252.  
  253. /*fpga_clock: fpga_clock {
  254. compatible = "fixed-clock";
  255. #clock-cells = <0>;
  256. clock-frequency = <200000000>;
  257. };*/
  258.  
  259. /*hdmi_clock: axi-clkgen@66000000 {
  260. compatible = "adi,axi-clkgen-1.00.a";
  261. reg = <0x66000000 0x10000>;
  262. #clock-cells = <0>;
  263. clocks = <&fpga_clock>;
  264. };*/
  265.  
  266. /*axi_hdmi@6c000000 {
  267. compatible = "adi,axi-hdmi-1.00.a";
  268. reg = <0x6c000000 0x10000>;
  269. encoder-slave = <&adv7511>;
  270. dmas = <&axi_vdma_0 0>;
  271. dma-names = "video";
  272. clocks = <&hdmi_clock>;
  273. };*/
  274.  
  275. /*axi_spdif_tx_0: axi-spdif-tx@0x75c00000 {
  276. compatible = "adi,axi-spdif-tx-1.00.a";
  277. reg = < 0x75c00000 0x1000 >;
  278. dmas = <&axi_dma_0 0>;
  279. dma-names = "tx";
  280. clock-frequency = <12288000>;
  281. };*/
  282.  
  283. /*adv7511_hdmi_snd: adv7511_hdmi_snd {
  284. compatible = "adv7511-hdmi-snd";
  285. audio-codec-adapter = <&axi_iic_0>;
  286. cpu-dai = <&axi_spdif_tx_0>;
  287. };*/
  288. };
  289. };
RAW Paste Data