library ieee;
use ieee.std_logic_1164.all;

entity part2 is
	port(w: in std_logic;
		 z: out std_logic);

end part2;

architecture behavior of part2 is
	type state_type is(A,B,C,D,E,F,G,H,I);
	signal y_Q,Y_D : state_type;        -- y_Q present state, Y_D next state
begin
	process (w,y_Q)                     -- State table
	begin
		z <= 0;
		case y_Q is
			when A =>
				if (w = '0') then
					Y_D <= B;
				else
					Y_D <= F;
				end if;
			when B =>
				if (w = '0') then
					Y_D <= C;
				else
					Y_D <= F;
				end if;
			when C =>
				if (w = '0') then
					Y_D <= D;
				else
					Y_D <= F;
				end if;
			when D =>
				if  (w = '0') then
					Y_D <= E;
				else
					Y_D <= F;
				end if;
			when E =>
				z <= 1;
				if (w = '0') then
					Y_D <= E;
				else
					Y_D <= F;
				end if;
			when F =>
				if (w = '0') then
					Y_D <= B;
				else
					Y_D <= G;
				end if;
			when G =>
				if (w = '0') then
					Y_D <= B;
				else
					Y_D <= G;
				end if;
			when H =>
				if (w = '0') then
					Y_D <= B;
				else
					Y_D <= I;
				end if;
			when I =>
				z <= 1;
				if (w = '0') then
					Y_D <= B;
				else
					Y_D <= I;
				end if;
		end case;
	end process;

	process(clock)                      -- State flip flops
	begin
		if rising_edge(clock) then
			y_Q <= Y_D;
		end if;
	end process;

end architecture behavior;