`timescale 1 ps/ 1 ps
module dd_vlg_tst();
// constants
// general purpose registers
// test vector input registers
reg clk;
reg [7:0] in;
reg reset;
// wires
wire [11:0]  bcd;
integer i = 0;

// assign statements (if any)
dd i1 (
// port map - connection between master ports and signals/registers
    .bcd(bcd),
    .clk(clk),
    .in(in),
    .reset(reset)
);
initial
begin
  #0 reset = 0;
  #0 clk = 0;
  #2 reset = 1;

  for(i = 0; i < 256; i=i+1)
  begin
      #10 in = i;
      #5 reset = 0;
      #15 reset = 1;
      $display("t=%3d ocekivano: %d, izlaz:%d%d%d \n",$time,i,bcd[11:8], bcd[7:4], bcd[3:0]);
  end
  $stop;
end

always
begin
  #2 clk = ~clk;
end
endmodule