library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;

entity rippleCarry_adder is
    generic (
        N : integer :=8
    );

    port (
         C_IN: IN STD_LOGIC;
        C_OUT: OUT STD_LOGIC;

          A,B: IN  SIGNED (0 to N-1);
            S: OUT SIGNED (0 to N-1)
    );
end entity;

architecture rtl of rippleCarry_adder is

    --INTERNAL SIGNALS
    signal c : STD_LOGIC_VECTOR (0 to N );--INTERNAL CARRY
    signal c_p : STD_LOGIC_VECTOR (0 to N-1); --used to initialize c vector
    signal s_i : SIGNED (0 to N-1);

    component fulladder port (
                A : in STD_LOGIC;
                B : in STD_LOGIC;
              Cin : in STD_LOGIC;
                S : out STD_LOGIC;
             Cout : out STD_LOGIC
     );
end component;


begin

    c_p <= (others => '0');
    c<= C_IN & c_p; --set it as c_in followed by zeros

    full_adder_gen: for i in 0 to N-1  generate
        full_adder_n: fulladder port map (
           Cin   => c(i),
           A     => A(i),
           B     => B(i),
           S     => S(i),
           Cout  => c(i+1)
       );

      C_OUT <= c(N); --the carry out of the ripple-carry adder is the carry out of the last full adder


    end generate;


end architecture;