module counter(input clk,
               input cmd,
               output reg [4:0] out = 0);

always @(posedge clk) begin

    if (0 == cmd) begin
        out = out + 1;

        if (31 == out)
       out = 0;
    end
    else
        if (0 == out)
            out = 29;
        else
            if (1 == out)
            out = 30;
        else
                    out = out - 2;
end
endmodule