kolos_wyswietlacz_7_segmentowy

entity program is
    PORT(
        DATA_D : in std_logic_vector(7 downto 0);
        CLK_WR : in std_logic;
        W0 : out std_logic_vector(6 downto 0);
        W1 : out std_logic_vector(6 downto 0);)
end entity

-- w naszym FPGA dody świecą się 0!

architecture Behavioral of program is
    signal BUF : std_logic_vector
    signal display_0 : std_logic_vector(6 downto 0);
    signal display_1 : std_logic_vector(6 downto 0);


    READ : process(CLK_WR)
            variable counter : integer := 0;
        begin
            if falling_edge(CLK_WR) then
                BUF <= DATA_D

            end if

end architecture