library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Rejestry is
port
(
            clk : in std_logic;
            DI : in signed (15 downto 0);
            BA : in signed (15 downto 0);
            Sbb : in signed (3 downto 0);
            Sbc : in signed (3 downto 0);
            Sba : in signed (3 downto 0);
            Sid : in signed (2 downto 0);
            Sa : in signed (1 downto 0);
            BB : out signed (15 downto 0);
            BC : out signed (15 downto 0);
            ADR : out signed (31 downto 0);
            IRout : out signed (15 downto 0)
);
end entity;

architecture rtl of Rejestry is
begin
process (clk, Sbb, Sbc, Sba, Sid, Sa, DI)
            variable IR, TMP, A, B, C, D, ES,DS,CS: signed (15 downto 0);
            variable AD, PC, SP, ATMP : signed (31 downto 0);
            begin
            if (clk'event and clk='1') then
            case Sid is
                when "001" => PC := PC + 1;
                when "010" => SP := SP + 1;
                when "011" => AD := AD + 1;
                when "101" => SP := SP + 1;
                when "110" => AD := AD + 1;
                when others => null;
            end case;
            case Sba is
                when "0000" => IR := BA;
                when "0001" => TMP := BA;
                when "0010" => A := BA;
                when "0011" => B := BA;
                when "0100" => C := BA;
                when "0101" => D := BA;
                when "0110" => ES := BA;
                when "0111" => DS := BA;
                when "1000" => CS := BA;
                when "1001" => AD := BA;
                when "1010" => PC := BA;
                when "1011" => SP := BA;
                when "1100" => ATMP := BA;
                when others => null;
            end case;
            end if;
            case Sbb is
                when "0000" => BB <= DI;
                when "0001" => BB <= TMP;
                when "0010" => BB <= A;
                when "0011" => BB <= B;
                when "0100" => BB <= C;
                when "0101" => BB <= D;
                when others => null;
            end case;
            case Sbc is
                when "0000" => BC <= DI;
                when "0001" => BC <= TMP;
                when "0010" => BC <= A;
                when "0011" => BC <= B;
                when "0100" => BC <= C;
                when "0101" => BC <= D;
                when others => null;
            end case;
            case Sa is
                when "000" => ADR <= AD;
                when "001" => ADR <= PC;
                when "010" => ADR <= SP;
                when "011" => ADR <= ATMP;
                when "100" => ADR <= ES;
                when "101" => ADR <= DS;
                when "110" => ADR <= CS;
            end case;
            IRout <= IR;
end process;
end rtl;