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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity updown is
- generic(width: integer := 8);
- port
- ( clk : IN STD_LOGIC;
- reset : IN STD_LOGIC;
- y : OUT STD_LOGIC_VECTOR(width-1 downto 0);
- dir : IN STD_LOGIC);
- end updown;
- architecture Behavioral of updown is
- signal counter: std_logic_vector(width-1 downto 0);
- begin
- process (clk, reset)
- begin
- if reset = '1' THEN
- counter <= "00000000";
- elsif (RISING_EDGE(clk)) then
- if(dir = '0') then
- counter <= counter + 1;
- else
- counter <= counter -1;
- end if;
- end if;
- end process;
- y <= counter;
- end Behavioral;
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