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Apr 26th, 2018
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VHDL 0.97 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5.  
  6. -- Uncomment the following library declaration if using
  7. -- arithmetic functions with Signed or Unsigned values
  8. --use IEEE.NUMERIC_STD.ALL;
  9.  
  10. -- Uncomment the following library declaration if instantiating
  11. -- any Xilinx primitives in this code.
  12. --library UNISIM;
  13. --use UNISIM.VComponents.all;
  14.  
  15. entity updown is
  16. generic(width:  integer := 8);
  17. port
  18.     (   clk :   IN  STD_LOGIC;
  19.         reset   :   IN STD_LOGIC;
  20.         y       :   OUT STD_LOGIC_VECTOR(width-1 downto 0);
  21.         dir :   IN STD_LOGIC);
  22.        
  23. end updown;
  24.  
  25. architecture Behavioral of updown is
  26. signal counter: std_logic_vector(width-1 downto 0);
  27.  
  28. begin
  29.     process (clk, reset)
  30.     begin
  31.         if reset = '1' THEN
  32.             counter <= "00000000";
  33.         elsif (RISING_EDGE(clk)) then
  34.             if(dir = '0') then
  35.                 counter <= counter + 1;
  36.             else
  37.                 counter <= counter -1;
  38.             end if;
  39.         end if;
  40.     end process;
  41.    
  42. y <= counter;
  43.  
  44. end Behavioral;
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