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  1. U-Boot 2012.10 (Mar 28 2021 - 23:36:32)Meraki MX64 Boot Kernel Loader
  2.  
  3. DEV ID = 0xcf1e
  4. PCIE CFG DEV ID = 0x8025
  5. OTP offset(0x8): 0x78f01c01
  6. OTP offset(0x9): 0xfe200818
  7. OTP offset(0xa): 0xc01b0
  8. OTP offset(0xb): 0x0
  9. OTP offset(0xc): 0x4a00000
  10. OTP offset(0xd): 0xffede230
  11. OTP offset(0xe): 0x1035d17f
  12. OTP offset(0xf): 0x4000
  13. NSP25 32bit DDR
  14. SKU ID = 0x0
  15. DDR type: DDR3
  16. MEMC 0 DDR speed = 800MHz
  17. ddr_init2: Calling soc_ddr40_set_shmoo_dram_config
  18. ddr_init2: Calling soc_ddr40_phy_calibrate
  19. C01. Check Power Up Reset_Bar
  20. C02. Config and Release PLL from reset
  21. C03. Poll PLL Lock
  22. C04. Calibrate ZQ (ddr40_phy_calib_zq)
  23. C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT
  24. C06. DDR40_PHY_DDR3_MISC
  25. C07. VDL Calibration
  26. C07.1
  27. C07.2
  28. C07.4
  29. C07.4.1
  30. C07.4.4
  31. VDL calibration result: 0x30000003 (cal_steps = 0)
  32. C07.4.5
  33. C07.4.6
  34. C07.5
  35. C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....
  36. C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....
  37. C10. Wait for Phy Ready
  38. Programming controller register
  39. ddr_init2: Calling soc_ddr40_shmoo_ctl
  40. Validate Shmoo parameters stored in flash ..... OK
  41. Press Ctrl-C to run Shmoo ..... Pressed.
  42. Do you want to run the Shmoo? [y/N] Y
  43. DDR_CTLR_T1
  44. E01. Reset Vref before Shmoo
  45. D04. Calibrate ZQ (ddr40_phy_calib_zq) before Shmoo
  46. D07. VDL Calibration before Shmoo
  47. VDL calibration result: 0x30000003 (cal_steps = 0)
  48. _soc_ddr_shmoo_prepare_for_shmoo: Enter
  49. (WL=0) data = 0x642001
  50. (WL=0) PLL_STATUS : LOCK_LOST = 0x0
  51. (WL=0) PLL_STATUS : LOCK = 0x1
  52. (WL=0) data = 0x1c24000
  53. (WL=0) ZQ_PVT_COMP_CTL : PD_COMP = 0x4
  54. (WL=0) ZQ_PVT_COMP_CTL : ND_COMP = 0x4
  55. (WL=0) data = 0x7
  56. (WL=0) PHY_WORD_LANE_READ_CONTROL : DQ_ODT_ENABLE = 0x1
  57. (WL=0) PHY_WORD_LANE_READ_CONTROL : DQ_ODT_LE_ADJ = 0x1
  58. (WL=0) PHY_WORD_LANE_READ_CONTROL : DQ_ODT_TE_ADJ = 0x1
  59. (WL=0) data = 0x0
  60. (WL=0) VDL_CALIBRATE : CALIB_FAST = 0x0
  61. (WL=0) VDL_CALIBRATE : CALIB_ONCE = 0x0
  62. (WL=0) VDL_CALIBRATE : CALIB_ALWAYS = 0x0
  63. (WL=0) VDL_CALIBRATE : CALIB_TEST = 0x0
  64. (WL=0) VDL_CALIBRATE : CALIB_CLOCKS = 0x0
  65. (WL=0) VDL_CALIBRATE : CALIB_BYTE = 0x0
  66. (WL=0) VDL_CALIBRATE : CALIB_PHYBIST = 0x0
  67. (WL=0) VDL_CALIBRATE : CALIB_FTM = 0x0
  68. (WL=0) VDL_CALIBRATE : CALIB_AUTO = 0x0
  69. (WL=0) VDL_CALIBRATE : CALIB_STEPS = 0x0
  70. (WL=0) VDL_CALIBRATE : CALIB_DQS_PAIR = 0x0
  71. (WL=0) VDL_CALIBRATE : CALIB_DQS_CLOCKS = 0x0
  72. (WL=0) VDL_CALIBRATE : CALIB_BIT_OFFSET = 0x0
  73. (WL=0) VDL_CALIBRATE : RD_EN_CAL = 0x0
  74. (WL=0) VDL_CALIBRATE : BIT_CAL = 0x0
  75. (WL=0) VDL_CALIBRATE : SET_MR_MPR = 0x0
  76. (WL=0) VDL_CALIBRATE : DQ0_ONLY = 0x0
  77. (WL=0) VDL_CALIBRATE : SET_WR_DQ = 0x0
  78. (WL=0) VDL_CALIBRATE : BIT_REFRESH = 0x0
  79. (WL=0) VDL_CALIBRATE : RD_DLY_CAL = 0x0
  80. (WL=0) VDL_CALIBRATE : EXIT_IN_SR = 0x0
  81. (WL=0) VDL_CALIBRATE : SKIP_RST = 0x0
  82. (WL=0) VDL_CALIBRATE : AUTO_INIT = 0x0
  83. (WL=0) VDL_CALIBRATE : USE_STRAPS = 0x0
  84. (WL=0) data = 0x30000003
  85. (WL=0) VDL_CALIB_STATUS : CALIB_LOCK = 0x1
  86. (WL=0) VDL_CALIB_STATUS : CALIB_IDLE = 0x1
  87. (WL=0) VDL_CALIB_STATUS : CALIB_BYTE_SEL = 0x0
  88. (WL=0) VDL_CALIB_STATUS : CALIB_BIT_OFFSET set if byte mode = 0x0
  89. (WL=0) NOTE: For single step calibration total result, please see below
  90. (WL=0) data = 0x13512ff
  91. (WL=0) VDL_DQ_CALIB_STATUS : DQ_CALIB_LOCK = 0x1
  92. (WL=0) VDL_DQ_CALIB_STATUS : DQS_CALIB_LOCK = 0x1
  93. (WL=0) VDL_DQ_CALIB_STATUS : DQS_CALIB_MODE DQS(1=pair) = 0x1
  94. (WL=0) VDL_DQ_CALIB_STATUS : DQS_CALIB_CLOCKS DQS(0=half bit) = 0x1
  95. (WL=0) VDL_DQ_CALIB_STATUS : DQ_CALIB_TOTAL DQ (steps) = 0x12
  96. (WL=0) VDL_DQ_CALIB_STATUS : DQS_CALIB_TOTAL DQS (steps) = 0x13
  97. (WL=0) data = 0x1301
  98. (WL=0) VDL_WR_CHAN_CALIB_STATUS : WR_CHAN_CALIB_LOCK = 0x1
  99. (WL=0) VDL_WR_CHAN_CALIB_STATUS : WR_CHAN_CALIB_BYTE_SEL (1=byte) = 0x0
  100. (WL=0) VDL_WR_CHAN_CALIB_STATUS : WR_CHAN_CALIB_CLOCKS (0=1/2bit) = 0x0
  101. (WL=0) VDL_WR_CHAN_CALIB_STATUS : WR_CHAN_CALIB_TOTAL (steps) = 0x13
  102. (WL=0) VDL_WR_CHAN_CALIB_STATUS : WR_CHAN_CALIB_BIT_OFFSET (in byte mode, settin g for bit vdl)= 0x0
  103. (WL=0) data = 0x2ff5
  104. (WL=0) VDL_RD_EN_CALIB_STATUS : RD_EN_CALIB_LOCK = 0x1
  105. (WL=0) VDL_RD_EN_CALIB_STATUS : RD_EN_CALIB_BYTE_SEL (1=byte) = 0x0
  106. (WL=0) VDL_RD_EN_CALIB_STATUS : RD_EN_CALIB_CLOCKS (0=1/2bit) = 0x1
  107. (WL=0) VDL_RD_EN_CALIB_STATUS : RD_EN_CALIB_TOTAL (steps) = 0x2f
  108. (WL=0) VDL_RD_EN_CALIB_STATUS : RD_EN_CALIB_BIT_OFFSET (in byte mode, setting fo r bit vdl)= 0x0
  109. (WL=0) VDL_CALIB_STATUS : NOT CALIB_LOCK
  110. iproc_get_ddr3_clock_mhz ndiv(0x80) mdiv(0x8) ddrclk(0x320)
  111. -----------------------------------------
  112. --- Single STEP Calibration ---
  113. -----------------------------------------
  114. (WL=0) VDL_CALIB_STATUS : CALIB_LOCK = 1
  115. (WL=0) VDL_CALIB_STATUS : CALIB_IDLE = 1
  116. (WL=0) VDL_CALIB_STATUS : 360'CALIB_TOTAL = 116 (steps)
  117. (WL=%f) VDL_CALIB_STATUS : 90' SALIB TOTAL = 0 (steps)
  118. (WL=0) VDL_CALIB_STATUS : 360' steps time = 1250 (ps)
  119. (WL=0) VDL_CALIB_STATUS : 90' step time = 43.103 (ps)
  120. (WL=0) VDL_CALIB_STATUS : Single step time = 10.775 (ps)
  121. sizeof(soc_ddr_shmoo_param_t) = 29c
  122. sal_memset
  123. sizeof(vref_word_shmoo) = 12b00
  124. BEGIN SHMOO
  125. BEFORE SHMOO: Type = 0 CI = 0 WL = 0
  126. Address = 0x004C Data = 0x300001D3 VDL CALIB STATUS
  127. Address = 0x0058 Data = 0x00002FF4 VDL RD EN CALIB STATUS
  128. Address = 0x0050 Data = 0x013512FC VDL DQ/DQS CALIB STATUS
  129. Address = 0x0054 Data = 0x00001300 VDL WR DQ CALIB STATUS
  130. Address = 0x0030 Data = 0x00000000 VDL OVRIDE BYTE CTL
  131. Address = 0x0034 Data = 0x00000000 VDL OVRIDE BIT C TL
  132. Address = 0x003C Data = 0x01C24000 ZQ PVT COMP CTL
  133. Address = 0x006C Data = 0x00000820 VREF DAC CONTROL
  134. Address = 0x0360 Data = 0x00000001 READ DATA DLY
  135. Address = 0x0200 Data = 0x00000000 VDL OVRIDE BYTE RD EN
  136. Address = 0x0274 Data = 0x00000000 VDL OVRIDE BYTE0 BIT RD EN
  137. Address = 0x0314 Data = 0x00000000 VDL OVRIDE BYTE1 BIT RD EN
  138. Address = 0x0234 Data = 0x00000000 VDL OVRIDE BYTE0 BIT0 R DQ
  139. Address = 0x02D4 Data = 0x00000000 VDL OVRIDE BYTE1 BIT0 R DQ
  140. Address = 0x0208 Data = 0x00000000 VDL OVRIDE BYTE0 R DQS
  141. Address = 0x02A8 Data = 0x00000000 VDL OVRIDE BYTE1 R DQS
  142. Address = 0x0204 Data = 0x00000000 VDL OVRIDE BYTE0 WR DQ
  143. Address = 0x0210 Data = 0x00000000 VDL OVRIDE BYTE0 BIT WR DQ
  144. Address = 0x02A4 Data = 0x00000000 VDL OVRIDE BYTE1 WR DQ
  145. Address = 0x02B0 Data = 0x00000000 VDL OVRIDE BYTE1 BIT WR DQ
  146. calib_steps: 191
  147. AFTER SHMOO: Type = 0 CI = 0 WL = 0
  148. Address = 0x004C Data = 0x300001D3 VDL CALIB STATUS
  149. Address = 0x0058 Data = 0x00002FF4 VDL RD EN CALIB STATUS
  150. Address = 0x0050 Data = 0x013512FC VDL DQ/DQS CALIB STATUS
  151. Address = 0x0054 Data = 0x00001300 VDL WR DQ CALIB STATUS
  152. Address = 0x0030 Data = 0x00000000 VDL OVRIDE BYTE CTL
  153. Address = 0x0034 Data = 0x00010028 VDL OVRIDE BIT C TL
  154. Address = 0x003C Data = 0x01C24000 ZQ PVT COMP CTL
  155. Address = 0x006C Data = 0x00000820 VREF DAC CONTROL
  156. Address = 0x0360 Data = 0x00000001 READ DATA DLY
  157. Address = 0x0200 Data = 0x00010017 VDL OVRIDE BYTE RD EN
  158. Address = 0x0274 Data = 0x00010017 VDL OVRIDE BYTE0 BIT RD EN
  159. Address = 0x0314 Data = 0x00010017 VDL OVRIDE BYTE1 BIT RD EN
  160. Address = 0x0234 Data = 0x00010012 VDL OVRIDE BYTE0 BIT0 R DQ
  161. Address = 0x02D4 Data = 0x00010012 VDL OVRIDE BYTE1 BIT0 R DQ
  162. Address = 0x0208 Data = 0x00010026 VDL OVRIDE BYTE0 R DQS
  163. Address = 0x02A8 Data = 0x00010026 VDL OVRIDE BYTE1 R DQS
  164. Address = 0x0204 Data = 0x00010000 VDL OVRIDE BYTE0 WR DQ
  165. Address = 0x0210 Data = 0x00010013 VDL OVRIDE BYTE0 BIT WR DQ
  166. Address = 0x02A4 Data = 0x00010000 VDL OVRIDE BYTE1 WR DQ
  167. Address = 0x02B0 Data = 0x00010013 VDL OVRIDE BYTE1 BIT WR DQ
  168.  
  169. BEFORE SHMOO: Type = 0 CI = 0 WL = 1
  170. Address = 0x004C Data = 0x300001D3 VDL CALIB STATUS
  171. Address = 0x0058 Data = 0x00002FF4 VDL RD EN CALIB STATUS
  172. Address = 0x0050 Data = 0x013512FC VDL DQ/DQS CALIB STATUS
  173. Address = 0x0054 Data = 0x00001300 VDL WR DQ CALIB STATUS
  174. Address = 0x0030 Data = 0x00000000 VDL OVRIDE BYTE CTL
  175. Address = 0x0034 Data = 0x00010028 VDL OVRIDE BIT C TL
  176. Address = 0x003C Data = 0x01C24000 ZQ PVT COMP CTL
  177. Address = 0x006C Data = 0x00000820 VREF DAC CONTROL
  178. Address = 0x0560 Data = 0x00000001 READ DATA DLY
  179. Address = 0x0400 Data = 0x00000000 VDL OVRIDE BYTE RD EN
  180. Address = 0x0474 Data = 0x00000000 VDL OVRIDE BYTE0 BIT RD EN
  181. Address = 0x0514 Data = 0x00000000 VDL OVRIDE BYTE1 BIT RD EN
  182. Address = 0x0434 Data = 0x00000000 VDL OVRIDE BYTE0 BIT0 R DQ
  183. Address = 0x04D4 Data = 0x00000000 VDL OVRIDE BYTE1 BIT0 R DQ
  184. Address = 0x0408 Data = 0x00000000 VDL OVRIDE BYTE0 R DQS
  185. Address = 0x04A8 Data = 0x00000000 VDL OVRIDE BYTE1 R DQS
  186. Address = 0x0404 Data = 0x00000000 VDL OVRIDE BYTE0 WR DQ
  187. Address = 0x0410 Data = 0x00000000 VDL OVRIDE BYTE0 BIT WR DQ
  188. Address = 0x04A4 Data = 0x00000000 VDL OVRIDE BYTE1 WR DQ
  189. Address = 0x04B0 Data = 0x00000000 VDL OVRIDE BYTE1 BIT WR DQ
  190. calib_steps: 191
  191. AFTER SHMOO: Type = 0 CI = 0 WL = 1
  192. Address = 0x004C Data = 0x300001D3 VDL CALIB STATUS
  193. Address = 0x0058 Data = 0x00002FF4 VDL RD EN CALIB STATUS
  194. Address = 0x0050 Data = 0x013512FC VDL DQ/DQS CALIB STATUS
  195. Address = 0x0054 Data = 0x00001300 VDL WR DQ CALIB STATUS
  196. Address = 0x0030 Data = 0x00000000 VDL OVRIDE BYTE CTL
  197. Address = 0x0034 Data = 0x00010028 VDL OVRIDE BIT C TL
  198. Address = 0x003C Data = 0x01C24000 ZQ PVT COMP CTL
  199. Address = 0x006C Data = 0x00000820 VREF DAC CONTROL
  200. Address = 0x0560 Data = 0x00000001 READ DATA DLY
  201. Address = 0x0400 Data = 0x00010017 VDL OVRIDE BYTE RD EN
  202. Address = 0x0474 Data = 0x00010017 VDL OVRIDE BYTE0 BIT RD EN
  203. Address = 0x0514 Data = 0x00010017 VDL OVRIDE BYTE1 BIT RD EN
  204. Address = 0x0434 Data = 0x00010012 VDL OVRIDE BYTE0 BIT0 R DQ
  205. Address = 0x04D4 Data = 0x00010012 VDL OVRIDE BYTE1 BIT0 R DQ
  206. Address = 0x0408 Data = 0x00010026 VDL OVRIDE BYTE0 R DQS
  207. Address = 0x04A8 Data = 0x00010026 VDL OVRIDE BYTE1 R DQS
  208. Address = 0x0404 Data = 0x00010000 VDL OVRIDE BYTE0 WR DQ
  209. Address = 0x0410 Data = 0x00010013 VDL OVRIDE BYTE0 BIT WR DQ
  210. Address = 0x04A4 Data = 0x00010000 VDL OVRIDE BYTE1 WR DQ
  211. Address = 0x04B0 Data = 0x00010013 VDL OVRIDE BYTE1 BIT WR DQ
  212.  
  213. BEFORE SHMOO: Type = 1 CI = 0 WL = 0
  214. Address = 0x004C Data = 0x300001D3 VDL CALIB STATUS
  215. Address = 0x0058 Data = 0x00002FF4 VDL RD EN CALIB STATUS
  216. Address = 0x0050 Data = 0x013512FC VDL DQ/DQS CALIB STATUS
  217. Address = 0x0054 Data = 0x00001300 VDL WR DQ CALIB STATUS
  218. Address = 0x0030 Data = 0x00000000 VDL OVRIDE BYTE CTL
  219. Address = 0x0034 Data = 0x00010028 VDL OVRIDE BIT C TL
  220. Address = 0x003C Data = 0x01C24000 ZQ PVT COMP CTL
  221. Address = 0x006C Data = 0x00000820 VREF DAC CONTROL
  222. Address = 0x0360 Data = 0x00000001 READ DATA DLY
  223. Address = 0x0200 Data = 0x00010017 VDL OVRIDE BYTE RD EN
  224. Address = 0x0274 Data = 0x00010017 VDL OVRIDE BYTE0 BIT RD EN
  225. Address = 0x0314 Data = 0x00010017 VDL OVRIDE BYTE1 BIT RD EN
  226. Address = 0x0234 Data = 0x00010012 VDL OVRIDE BYTE0 BIT0 R DQ
  227. Address = 0x02D4 Data = 0x00010012 VDL OVRIDE BYTE1 BIT0 R DQ
  228. Address = 0x0208 Data = 0x00010026 VDL OVRIDE BYTE0 R DQS
  229. Address = 0x02A8 Data = 0x00010026 VDL OVRIDE BYTE1 R DQS
  230. Address = 0x0204 Data = 0x00010000 VDL OVRIDE BYTE0 WR DQ
  231. Address = 0x0210 Data = 0x00010013 VDL OVRIDE BYTE0 BIT WR DQ
  232. Address = 0x02A4 Data = 0x00010000 VDL OVRIDE BYTE1 WR DQ
  233. Address = 0x02B0 Data = 0x00010013 VDL OVRIDE BYTE1 BIT WR DQ
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  464. ▒Ab▒{▒K▒ڛ]▒d
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  486. ▒Ab▒{▒K▒ڛ]▒d
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  489. ▒9863>(▒<▒S▒▒▒▒▒▒▒▒▒`63
  490. ▒Ab▒{▒K▒ڛ]▒d
  491. ▒9863>(▒<▒S▒▒▒▒▒▒▒▒▒`63
  492. ▒Ab▒{▒K▒ڛ]▒d
  493. ▒9863>(▒<▒S▒▒▒▒▒▒▒▒▒`63
  494. ▒Ab▒{▒K▒ڛ]▒d
  495. ▒9863>(▒<▒S▒▒▒▒▒▒▒▒▒`63
  496. ▒Ab▒{▒K▒ڛ]▒d
  497.  
  498. Switching to RD_DATA_DELAY Step : 3 (WL = 0)
  499. Switching to RD_DQ Step (Byte 0) : 23
  500. Switching to RD_DQ Step (Byte 1) : 22
  501.  
  502.  
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