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  1. module sekwencje
  2. (
  3. input x,reset,clk,
  4. output reg y,
  5. output led
  6. );
  7. wire slow_clk;
  8. reg [26:0] div_clk;
  9. always@(posedge clk, posedge reset)
  10.     if (reset)
  11.         div_clk <= 0;
  12.     else
  13.         div_clk <= div_clk+1;
  14. assign slow_clk = div_clk[26];
  15.  
  16. assign led = slow_clk;
  17.  
  18. reg[3:0] aut_reg, aut_next;
  19. localparam s0=0,s1=1,s2=2,s3=3,s4=4;
  20.  
  21. always @(*)
  22.     case (aut_reg)
  23.         s0: if (x) aut_next=s0;
  24.                 else aut_next=s1;
  25.        
  26.         s1: if (x) aut_next=s0;
  27.                 else aut_next=s2;
  28.        
  29.         s2: if (x) aut_next=s0;
  30.                 else aut_next=s3;
  31.        
  32.         s3: if (x) aut_next=s4;
  33.                 else aut_next=s1;
  34.        
  35.         s4: if (x) aut_next=s0;
  36.                 else aut_next=s1;
  37.                
  38.         default: aut_next=s0;
  39.     endcase
  40.  
  41. always@(posedge slow_clk, posedge reset)
  42.     if (reset)
  43.         aut_reg<=s0;
  44.     else
  45.         aut_reg<=aut_next;
  46. always@(*)
  47.     if (aut_reg==s4) y=1;
  48.     else y=0;
  49.     endmodule
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