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Nov 8th, 2018
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VHDL 2.59 KB | None | 0 0
  1. LIBRARY ieee;
  2. USE ieee.std_logic_1164.ALL;
  3.  
  4. -- Uncomment the following library declaration if using
  5. -- arithmetic functions with Signed or Unsigned values
  6. --USE ieee.numeric_std.ALL;
  7.  
  8. ENTITY cputest IS
  9. END cputest;
  10.  
  11. ARCHITECTURE behavior OF cputest IS
  12.  
  13.     -- Component Declaration for the Unit Under Test (UUT)
  14.  
  15.     COMPONENT CPU
  16.     PORT(
  17.                 Ext_Data_Bus : inout  STD_LOGIC_VECTOR (31 downto 0);
  18.                 Ext_Address_Bus : out  STD_LOGIC_VECTOR (31 downto 0);
  19.                 Ext_Address_Read : out  STD_LOGIC;
  20.                 Ext_Address_Write : out  STD_LOGIC);
  21.     END COMPONENT;
  22.  
  23.  
  24.    --Inputs
  25.     signal databus : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
  26.  
  27.      --Outputs
  28.     signal addressbus : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
  29.     signal addressread : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
  30.     signal addresswrite : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
  31.    -- No clocks detected in port list. Replace <clock> below with
  32.    -- appropriate port name
  33.  
  34. --   constant <clock>_period : time := 10 ns;
  35.  
  36. BEGIN
  37.  
  38.     -- Instantiate the Unit Under Test (UUT)
  39.    uut: CPU PORT MAP (
  40.     Ext_Data_Bus => databus;
  41.     Ext_Address_Bus => addressbus;
  42.     Ext_Address_Read => addressread;
  43.     Ext_Address_Write => addresswrite;
  44.         );
  45.  
  46.    -- Clock process definitions
  47. --  <clock>_process :process
  48. --   begin
  49. --        <clock> <= '0';
  50. --        wait for <clock>_period/2;
  51. --        <clock> <= '1';
  52. --        wait for <clock>_period/2;
  53. --   end process;
  54.  
  55.  
  56.    -- Stimulus process
  57.    stim_proc: process
  58.    begin
  59.        while ('1' = '1') loop
  60.         if (addressbus = "00000000000000000000000000000000") then--0
  61.             databus <= "10001110010010110000000100101100";--LW $t3, 300($s2)
  62.             wait 100 ns;
  63.         elsif (addressbus = "00000000000000000000000000000100") then--4
  64.             databus <= "10101110111011100000000110010000";--SW $t6, 400($s7)
  65.                     wait for 100 ns;
  66.         elsif (addressbus = "00000000000000000000000000001000") then--8
  67.             databus <= "00000001011100010110100000100000";--add $t5, $t3, $s1)
  68.                     wait for 100 ns;
  69.         elsif (addressbus = "00000000000000000000000000001100") then--12
  70.             databus <= "00010110110011010000000000110001";--bne $s6, $t5, 200
  71.             wait for 100 ns;
  72.         elsif (addressbus = "00000000000000000000000000010000") then--16
  73.             databus <= "00010010111110000000000000011000";--beq $s7, $t8, 100
  74.                 wait for 100 ns;
  75.         elsif (addressbus = "00000000000000000000000000010100") then--20
  76.             databus <= "00110101001100100000000010100001";--ori $s2, $t1, 0xA1
  77.                     wait for 100 ns;
  78.        end loop;
  79.    end process;
  80.  
  81. END;
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