4.1.1)

a) Since AND is an ALU op:

BSrc looks for the register.
OpSel tells ALU to AND.
MemW is false.
RegW is true, so process is writing to reg Rd
WBSrc uses ALU output as its data.
RegDst is reg Rd.
PCSrc is 0.

4.1.2)

a) registers, mux, mem, alu, pc

4.1.3)

a) data memory and branch

***

4.7.1)

Sign-Extend:
0000 0000 0000 0000 0000 0000 0001 0100
Jump shift-left 2
0001 1000 1000 0000 0000 0101 0000

4.7.2)

Because it is Sw, ALUOP = 00, and input of ALU control is 0010 (AND).

4.7.3)

Since it's not a branch or a jump, the new PC address is itself plus 4.

4.7.4)

Reg: mux X
ALU: mux 0x00000014
Mem/ALU: mux X
Branch: mux PC + 4
Jump: mux PC + 4

4.7.5)

ALU: -3 and 0x00000014
PC: add PC and 4
Branch: add PC+4 and 0x00000014

4.7.6)

RegWrite = 0
Write Register = x
Write Data = x
Reg A = 3
Reg B = 2

***

3) LI I-TYPE

RegDst: 	0
ALUSrc: 	1
ALU Op1: 	10
Branch: 	1
MemtoReg: 	0
RegWrite: 	X
MemRead: 	X
MemWrite: 	X

4) LUI I-TYPE

RegDst: 	0
ALUSrc: 	X
ALU Op: 	X
Branch: 	0
LuiCtr: 	1
MemtoReg: 	X
RegWrite: 	1
MemRead: 	X
MemWrite: 	0

5) JAL J-TYPE

RegDst: 	10
ALUSrc: 	X
ALU Op: 	X
Branch: 	0
Jump:		1
MemtoReg: 	10
RegWrite: 	1
MemRead: 	0
MemWrite: 	0

6) JR R-TYPE

RegDst: 	X
ALUSrc: 	X
ALU Op: 	X
Branch: 	0
Jump:		1
MemtoReg: 	X
RegWrite: 	0
MemRead: 	X
MemWrite: 	0